Simon Glass | 268eefd | 2014-11-12 22:42:28 -0700 | [diff] [blame] | 1 | /* |
| 2 | * From Coreboot src/southbridge/intel/bd82x6x/early_me.c |
| 3 | * |
| 4 | * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. |
| 5 | * |
| 6 | * SPDX-License-Identifier: GPL-2.0 |
| 7 | */ |
| 8 | |
| 9 | #include <common.h> |
Simon Glass | 37a91ff | 2016-01-17 16:11:50 -0700 | [diff] [blame] | 10 | #include <dm.h> |
Simon Glass | 268eefd | 2014-11-12 22:42:28 -0700 | [diff] [blame] | 11 | #include <errno.h> |
| 12 | #include <asm/pci.h> |
Simon Glass | 43a5034 | 2016-01-17 16:11:58 -0700 | [diff] [blame] | 13 | #include <asm/cpu.h> |
Simon Glass | 268eefd | 2014-11-12 22:42:28 -0700 | [diff] [blame] | 14 | #include <asm/processor.h> |
| 15 | #include <asm/arch/me.h> |
| 16 | #include <asm/arch/pch.h> |
| 17 | #include <asm/io.h> |
| 18 | |
| 19 | static const char *const me_ack_values[] = { |
| 20 | [ME_HFS_ACK_NO_DID] = "No DID Ack received", |
| 21 | [ME_HFS_ACK_RESET] = "Non-power cycle reset", |
| 22 | [ME_HFS_ACK_PWR_CYCLE] = "Power cycle reset", |
| 23 | [ME_HFS_ACK_S3] = "Go to S3", |
| 24 | [ME_HFS_ACK_S4] = "Go to S4", |
| 25 | [ME_HFS_ACK_S5] = "Go to S5", |
| 26 | [ME_HFS_ACK_GBL_RESET] = "Global Reset", |
| 27 | [ME_HFS_ACK_CONTINUE] = "Continue to boot" |
| 28 | }; |
| 29 | |
Simon Glass | 37a91ff | 2016-01-17 16:11:50 -0700 | [diff] [blame] | 30 | int intel_early_me_init(struct udevice *me_dev) |
Simon Glass | 268eefd | 2014-11-12 22:42:28 -0700 | [diff] [blame] | 31 | { |
| 32 | int count; |
| 33 | struct me_uma uma; |
| 34 | struct me_hfs hfs; |
| 35 | |
| 36 | debug("Intel ME early init\n"); |
| 37 | |
| 38 | /* Wait for ME UMA SIZE VALID bit to be set */ |
| 39 | for (count = ME_RETRY; count > 0; --count) { |
Simon Glass | 37a91ff | 2016-01-17 16:11:50 -0700 | [diff] [blame] | 40 | pci_read_dword_ptr(me_dev, &uma, PCI_ME_UMA); |
Simon Glass | 268eefd | 2014-11-12 22:42:28 -0700 | [diff] [blame] | 41 | if (uma.valid) |
| 42 | break; |
| 43 | udelay(ME_DELAY); |
| 44 | } |
| 45 | if (!count) { |
| 46 | printf("ERROR: ME is not ready!\n"); |
| 47 | return -EBUSY; |
| 48 | } |
| 49 | |
| 50 | /* Check for valid firmware */ |
Simon Glass | 37a91ff | 2016-01-17 16:11:50 -0700 | [diff] [blame] | 51 | pci_read_dword_ptr(me_dev, &hfs, PCI_ME_HFS); |
Simon Glass | 268eefd | 2014-11-12 22:42:28 -0700 | [diff] [blame] | 52 | if (hfs.fpt_bad) { |
| 53 | printf("WARNING: ME has bad firmware\n"); |
| 54 | return -EBADF; |
| 55 | } |
| 56 | |
| 57 | debug("Intel ME firmware is ready\n"); |
| 58 | |
| 59 | return 0; |
| 60 | } |
| 61 | |
Simon Glass | 37a91ff | 2016-01-17 16:11:50 -0700 | [diff] [blame] | 62 | int intel_early_me_uma_size(struct udevice *me_dev) |
Simon Glass | 268eefd | 2014-11-12 22:42:28 -0700 | [diff] [blame] | 63 | { |
| 64 | struct me_uma uma; |
| 65 | |
Simon Glass | 37a91ff | 2016-01-17 16:11:50 -0700 | [diff] [blame] | 66 | pci_read_dword_ptr(me_dev, &uma, PCI_ME_UMA); |
Simon Glass | 268eefd | 2014-11-12 22:42:28 -0700 | [diff] [blame] | 67 | if (uma.valid) { |
| 68 | debug("ME: Requested %uMB UMA\n", uma.size); |
| 69 | return uma.size; |
| 70 | } |
| 71 | |
| 72 | debug("ME: Invalid UMA size\n"); |
| 73 | return -EINVAL; |
| 74 | } |
| 75 | |
Simon Glass | 37a91ff | 2016-01-17 16:11:50 -0700 | [diff] [blame] | 76 | static inline void set_global_reset(struct udevice *dev, int enable) |
Simon Glass | 268eefd | 2014-11-12 22:42:28 -0700 | [diff] [blame] | 77 | { |
| 78 | u32 etr3; |
| 79 | |
Simon Glass | 37a91ff | 2016-01-17 16:11:50 -0700 | [diff] [blame] | 80 | dm_pci_read_config32(dev, ETR3, &etr3); |
Simon Glass | 268eefd | 2014-11-12 22:42:28 -0700 | [diff] [blame] | 81 | |
| 82 | /* Clear CF9 Without Resume Well Reset Enable */ |
| 83 | etr3 &= ~ETR3_CWORWRE; |
| 84 | |
| 85 | /* CF9GR indicates a Global Reset */ |
| 86 | if (enable) |
| 87 | etr3 |= ETR3_CF9GR; |
| 88 | else |
| 89 | etr3 &= ~ETR3_CF9GR; |
| 90 | |
Simon Glass | 37a91ff | 2016-01-17 16:11:50 -0700 | [diff] [blame] | 91 | dm_pci_write_config32(dev, ETR3, etr3); |
Simon Glass | 268eefd | 2014-11-12 22:42:28 -0700 | [diff] [blame] | 92 | } |
| 93 | |
Simon Glass | 37a91ff | 2016-01-17 16:11:50 -0700 | [diff] [blame] | 94 | int intel_early_me_init_done(struct udevice *dev, struct udevice *me_dev, |
| 95 | uint status) |
Simon Glass | 268eefd | 2014-11-12 22:42:28 -0700 | [diff] [blame] | 96 | { |
Simon Glass | 268eefd | 2014-11-12 22:42:28 -0700 | [diff] [blame] | 97 | int count; |
| 98 | u32 mebase_l, mebase_h; |
| 99 | struct me_hfs hfs; |
| 100 | struct me_did did = { |
| 101 | .init_done = ME_INIT_DONE, |
| 102 | .status = status |
| 103 | }; |
| 104 | |
| 105 | /* MEBASE from MESEG_BASE[35:20] */ |
Simon Glass | 37a91ff | 2016-01-17 16:11:50 -0700 | [diff] [blame] | 106 | dm_pci_read_config32(PCH_DEV, PCI_CPU_MEBASE_L, &mebase_l); |
| 107 | dm_pci_read_config32(PCH_DEV, PCI_CPU_MEBASE_H, &mebase_h); |
Simon Glass | 268eefd | 2014-11-12 22:42:28 -0700 | [diff] [blame] | 108 | mebase_h &= 0xf; |
| 109 | did.uma_base = (mebase_l >> 20) | (mebase_h << 12); |
| 110 | |
| 111 | /* Send message to ME */ |
| 112 | debug("ME: Sending Init Done with status: %d, UMA base: 0x%04x\n", |
| 113 | status, did.uma_base); |
| 114 | |
Simon Glass | 37a91ff | 2016-01-17 16:11:50 -0700 | [diff] [blame] | 115 | pci_write_dword_ptr(me_dev, &did, PCI_ME_H_GS); |
Simon Glass | 268eefd | 2014-11-12 22:42:28 -0700 | [diff] [blame] | 116 | |
| 117 | /* Must wait for ME acknowledgement */ |
| 118 | for (count = ME_RETRY; count > 0; --count) { |
Simon Glass | 37a91ff | 2016-01-17 16:11:50 -0700 | [diff] [blame] | 119 | pci_read_dword_ptr(me_dev, &hfs, PCI_ME_HFS); |
Simon Glass | 268eefd | 2014-11-12 22:42:28 -0700 | [diff] [blame] | 120 | if (hfs.bios_msg_ack) |
| 121 | break; |
| 122 | udelay(ME_DELAY); |
| 123 | } |
| 124 | if (!count) { |
| 125 | printf("ERROR: ME failed to respond\n"); |
Simon Glass | 37a91ff | 2016-01-17 16:11:50 -0700 | [diff] [blame] | 126 | return -ETIMEDOUT; |
Simon Glass | 268eefd | 2014-11-12 22:42:28 -0700 | [diff] [blame] | 127 | } |
| 128 | |
| 129 | /* Return the requested BIOS action */ |
| 130 | debug("ME: Requested BIOS Action: %s\n", me_ack_values[hfs.ack_data]); |
| 131 | |
| 132 | /* Check status after acknowledgement */ |
Simon Glass | b67be7e | 2016-03-11 22:07:00 -0700 | [diff] [blame] | 133 | intel_me_status(me_dev); |
Simon Glass | 268eefd | 2014-11-12 22:42:28 -0700 | [diff] [blame] | 134 | |
Simon Glass | 268eefd | 2014-11-12 22:42:28 -0700 | [diff] [blame] | 135 | switch (hfs.ack_data) { |
| 136 | case ME_HFS_ACK_CONTINUE: |
| 137 | /* Continue to boot */ |
| 138 | return 0; |
| 139 | case ME_HFS_ACK_RESET: |
| 140 | /* Non-power cycle reset */ |
Simon Glass | 37a91ff | 2016-01-17 16:11:50 -0700 | [diff] [blame] | 141 | set_global_reset(dev, 0); |
Simon Glass | 1375e9a | 2015-04-28 20:11:30 -0600 | [diff] [blame] | 142 | reset_cpu(0); |
Simon Glass | 268eefd | 2014-11-12 22:42:28 -0700 | [diff] [blame] | 143 | break; |
| 144 | case ME_HFS_ACK_PWR_CYCLE: |
| 145 | /* Power cycle reset */ |
Simon Glass | 37a91ff | 2016-01-17 16:11:50 -0700 | [diff] [blame] | 146 | set_global_reset(dev, 0); |
Simon Glass | 1375e9a | 2015-04-28 20:11:30 -0600 | [diff] [blame] | 147 | x86_full_reset(); |
Simon Glass | 268eefd | 2014-11-12 22:42:28 -0700 | [diff] [blame] | 148 | break; |
| 149 | case ME_HFS_ACK_GBL_RESET: |
| 150 | /* Global reset */ |
Simon Glass | 37a91ff | 2016-01-17 16:11:50 -0700 | [diff] [blame] | 151 | set_global_reset(dev, 1); |
Simon Glass | 1375e9a | 2015-04-28 20:11:30 -0600 | [diff] [blame] | 152 | x86_full_reset(); |
Simon Glass | 268eefd | 2014-11-12 22:42:28 -0700 | [diff] [blame] | 153 | break; |
| 154 | case ME_HFS_ACK_S3: |
| 155 | case ME_HFS_ACK_S4: |
| 156 | case ME_HFS_ACK_S5: |
| 157 | break; |
| 158 | } |
| 159 | |
Simon Glass | 37a91ff | 2016-01-17 16:11:50 -0700 | [diff] [blame] | 160 | return -EINVAL; |
Simon Glass | 268eefd | 2014-11-12 22:42:28 -0700 | [diff] [blame] | 161 | } |
Simon Glass | 37a91ff | 2016-01-17 16:11:50 -0700 | [diff] [blame] | 162 | |
| 163 | static const struct udevice_id ivybridge_syscon_ids[] = { |
Simon Glass | 43a5034 | 2016-01-17 16:11:58 -0700 | [diff] [blame] | 164 | { .compatible = "intel,me", .data = X86_SYSCON_ME }, |
Simon Glass | a75abeb | 2016-01-17 16:11:59 -0700 | [diff] [blame] | 165 | { .compatible = "intel,gma", .data = X86_SYSCON_GMA }, |
Simon Glass | 37a91ff | 2016-01-17 16:11:50 -0700 | [diff] [blame] | 166 | { } |
| 167 | }; |
| 168 | |
| 169 | U_BOOT_DRIVER(syscon_intel_me) = { |
| 170 | .name = "intel_me_syscon", |
| 171 | .id = UCLASS_SYSCON, |
| 172 | .of_match = ivybridge_syscon_ids, |
| 173 | }; |