blob: 2cf47125d433c1f99c23aa803cf1d9d6c622963b [file] [log] [blame]
Michal Simek04b7e622015-01-15 10:01:51 +01001/*
2 * (C) Copyright 2014 - 2015 Xilinx, Inc.
3 * Michal Simek <michal.simek@xilinx.com>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#include <common.h>
9#include <netdev.h>
Michal Simekb216cc12015-07-23 13:27:40 +020010#include <ahci.h>
11#include <scsi.h>
Michal Simek04b7e622015-01-15 10:01:51 +010012#include <asm/arch/hardware.h>
13#include <asm/arch/sys_proto.h>
14#include <asm/io.h>
Siva Durga Prasad Paladuguba1f68e2015-08-04 13:03:26 +053015#include <usb.h>
16#include <dwc3-uboot.h>
Michal Simek04b7e622015-01-15 10:01:51 +010017
18DECLARE_GLOBAL_DATA_PTR;
19
20int board_init(void)
21{
Michal Simekfb7242d2015-06-22 14:31:06 +020022 printf("EL Level:\tEL%d\n", current_el());
23
Michal Simek04b7e622015-01-15 10:01:51 +010024 return 0;
25}
26
27int board_early_init_r(void)
28{
29 u32 val;
30
31 val = readl(&crlapb_base->timestamp_ref_ctrl);
32 val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
33 writel(val, &crlapb_base->timestamp_ref_ctrl);
34
35 /* Program freq register in System counter and enable system counter */
36 writel(gd->cpu_clk, &iou_scntr->base_frequency_id_register);
37 writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG |
38 ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
39 &iou_scntr->counter_control_register);
40
41 return 0;
42}
43
44int dram_init(void)
45{
46 gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
47
48 return 0;
49}
50
51int timer_init(void)
52{
53 return 0;
54}
55
56void reset_cpu(ulong addr)
57{
58}
59
Michal Simekb216cc12015-07-23 13:27:40 +020060#ifdef CONFIG_SCSI_AHCI_PLAT
61void scsi_init(void)
62{
63 ahci_init((void __iomem *)ZYNQMP_SATA_BASEADDR);
64 scsi_scan(1);
65}
66#endif
67
Michal Simek04b7e622015-01-15 10:01:51 +010068int board_late_init(void)
69{
70 u32 reg = 0;
71 u8 bootmode;
72
73 reg = readl(&crlapb_base->boot_mode);
74 bootmode = reg & BOOT_MODES_MASK;
75
76 switch (bootmode) {
77 case SD_MODE:
Michal Simek02d66cd2015-04-15 15:02:28 +020078 case EMMC_MODE:
Michal Simek04b7e622015-01-15 10:01:51 +010079 setenv("modeboot", "sdboot");
80 break;
81 default:
82 printf("Invalid Boot Mode:0x%x\n", bootmode);
83 break;
84 }
85
86 return 0;
87}
Siva Durga Prasad Paladugu650e0a32015-08-04 13:01:05 +053088
89int checkboard(void)
90{
91 puts("Board:\tXilinx ZynqMP\n");
92 return 0;
93}
Siva Durga Prasad Paladuguba1f68e2015-08-04 13:03:26 +053094
95#ifdef CONFIG_USB_DWC3
96static struct dwc3_device dwc3_device_data = {
97 .maximum_speed = USB_SPEED_HIGH,
98 .base = ZYNQMP_USB0_XHCI_BASEADDR,
99 .dr_mode = USB_DR_MODE_PERIPHERAL,
100 .index = 0,
101};
102
103int usb_gadget_handle_interrupts(void)
104{
105 dwc3_uboot_handle_interrupt(0);
106 return 0;
107}
108
109int board_usb_init(int index, enum usb_init_type init)
110{
111 return dwc3_uboot_init(&dwc3_device_data);
112}
113
114int board_usb_cleanup(int index, enum usb_init_type init)
115{
116 dwc3_uboot_exit(index);
117 return 0;
118}
119#endif