| Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| TsiChung Liew | 7f1a046 | 2008-10-21 10:03:07 +0000 | [diff] [blame] | 2 | /* |
| 3 | * Edge Port Memory Map |
| 4 | * |
| 5 | * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. |
| 6 | * TsiChung Liew (Tsi-Chung.Liew@freescale.com) |
| TsiChung Liew | 7f1a046 | 2008-10-21 10:03:07 +0000 | [diff] [blame] | 7 | */ |
| 8 | |
| 9 | #ifndef __EPORT_H__ |
| 10 | #define __EPORT_H__ |
| 11 | |
| 12 | /* Edge Port Module (EPORT) */ |
| 13 | typedef struct eport { |
| 14 | #ifdef CONFIG_MCF547x_8x |
| 15 | u16 par; /* 0x00 */ |
| 16 | u16 res0; /* 0x02 */ |
| 17 | u8 ddr; /* 0x04 */ |
| 18 | u8 ier; /* 0x05 */ |
| 19 | u16 res1; /* 0x06 */ |
| 20 | u8 dr; /* 0x08 */ |
| 21 | u8 pdr; /* 0x09 */ |
| 22 | u16 res2; /* 0x0A */ |
| 23 | u8 fr; /* 0x0C */ |
| 24 | u8 res3[3]; /* 0x0D */ |
| 25 | #else |
| 26 | u16 par; /* 0x00 Pin Assignment */ |
| 27 | u8 ddr; /* 0x02 Data Direction */ |
| 28 | u8 ier; /* 0x03 Interrupt Enable */ |
| 29 | u8 dr; /* 0x04 Data */ |
| 30 | u8 pdr; /* 0x05 Pin Data */ |
| 31 | u8 fr; /* 0x06 Flag */ |
| 32 | u8 res0; |
| 33 | #endif |
| 34 | } eport_t; |
| 35 | |
| 36 | /* EPPAR */ |
| 37 | #define EPORT_PAR_EPPA1(x) (((x)&0x0003)<<2) |
| 38 | #define EPORT_PAR_EPPA2(x) (((x)&0x0003)<<4) |
| 39 | #define EPORT_PAR_EPPA3(x) (((x)&0x0003)<<6) |
| 40 | #define EPORT_PAR_EPPA4(x) (((x)&0x0003)<<8) |
| 41 | #define EPORT_PAR_EPPA5(x) (((x)&0x0003)<<10) |
| 42 | #define EPORT_PAR_EPPA6(x) (((x)&0x0003)<<12) |
| 43 | #define EPORT_PAR_EPPA7(x) (((x)&0x0003)<<14) |
| 44 | #define EPORT_PAR_LEVEL (0) |
| 45 | #define EPORT_PAR_RISING (1) |
| 46 | #define EPORT_PAR_FALLING (2) |
| 47 | #define EPORT_PAR_BOTH (3) |
| 48 | #define EPORT_PAR_EPPA7_LEVEL (0x0000) |
| 49 | #define EPORT_PAR_EPPA7_RISING (0x4000) |
| 50 | #define EPORT_PAR_EPPA7_FALLING (0x8000) |
| 51 | #define EPORT_PAR_EPPA7_BOTH (0xC000) |
| 52 | #define EPORT_PAR_EPPA6_LEVEL (0x0000) |
| 53 | #define EPORT_PAR_EPPA6_RISING (0x1000) |
| 54 | #define EPORT_PAR_EPPA6_FALLING (0x2000) |
| 55 | #define EPORT_PAR_EPPA6_BOTH (0x3000) |
| 56 | #define EPORT_PAR_EPPA5_LEVEL (0x0000) |
| 57 | #define EPORT_PAR_EPPA5_RISING (0x0400) |
| 58 | #define EPORT_PAR_EPPA5_FALLING (0x0800) |
| 59 | #define EPORT_PAR_EPPA5_BOTH (0x0C00) |
| 60 | #define EPORT_PAR_EPPA4_LEVEL (0x0000) |
| 61 | #define EPORT_PAR_EPPA4_RISING (0x0100) |
| 62 | #define EPORT_PAR_EPPA4_FALLING (0x0200) |
| 63 | #define EPORT_PAR_EPPA4_BOTH (0x0300) |
| 64 | #define EPORT_PAR_EPPA3_LEVEL (0x0000) |
| 65 | #define EPORT_PAR_EPPA3_RISING (0x0040) |
| 66 | #define EPORT_PAR_EPPA3_FALLING (0x0080) |
| 67 | #define EPORT_PAR_EPPA3_BOTH (0x00C0) |
| 68 | #define EPORT_PAR_EPPA2_LEVEL (0x0000) |
| 69 | #define EPORT_PAR_EPPA2_RISING (0x0010) |
| 70 | #define EPORT_PAR_EPPA2_FALLING (0x0020) |
| 71 | #define EPORT_PAR_EPPA2_BOTH (0x0030) |
| 72 | #define EPORT_PAR_EPPA1_LEVEL (0x0000) |
| 73 | #define EPORT_PAR_EPPA1_RISING (0x0004) |
| 74 | #define EPORT_PAR_EPPA1_FALLING (0x0008) |
| 75 | #define EPORT_PAR_EPPA1_BOTH (0x000C) |
| 76 | |
| 77 | /* EPDDR */ |
| 78 | #define EPORT_DDR_EPDD1 (0x02) |
| 79 | #define EPORT_DDR_EPDD2 (0x04) |
| 80 | #define EPORT_DDR_EPDD3 (0x08) |
| 81 | #define EPORT_DDR_EPDD4 (0x10) |
| 82 | #define EPORT_DDR_EPDD5 (0x20) |
| 83 | #define EPORT_DDR_EPDD6 (0x40) |
| 84 | #define EPORT_DDR_EPDD7 (0x80) |
| 85 | |
| 86 | /* EPIER */ |
| 87 | #define EPORT_IER_EPIE1 (0x02) |
| 88 | #define EPORT_IER_EPIE2 (0x04) |
| 89 | #define EPORT_IER_EPIE3 (0x08) |
| 90 | #define EPORT_IER_EPIE4 (0x10) |
| 91 | #define EPORT_IER_EPIE5 (0x20) |
| 92 | #define EPORT_IER_EPIE6 (0x40) |
| 93 | #define EPORT_IER_EPIE7 (0x80) |
| 94 | |
| 95 | /* EPDR */ |
| 96 | #define EPORT_DR_EPD1 (0x02) |
| 97 | #define EPORT_DR_EPD2 (0x04) |
| 98 | #define EPORT_DR_EPD3 (0x08) |
| 99 | #define EPORT_DR_EPD4 (0x10) |
| 100 | #define EPORT_DR_EPD5 (0x20) |
| 101 | #define EPORT_DR_EPD6 (0x40) |
| 102 | #define EPORT_DR_EPD7 (0x80) |
| 103 | |
| 104 | /* EPPDR */ |
| 105 | #define EPORT_PDR_EPPD1 (0x02) |
| 106 | #define EPORT_PDR_EPPD2 (0x04) |
| 107 | #define EPORT_PDR_EPPD3 (0x08) |
| 108 | #define EPORT_PDR_EPPD4 (0x10) |
| 109 | #define EPORT_PDR_EPPD5 (0x20) |
| 110 | #define EPORT_PDR_EPPD6 (0x40) |
| 111 | #define EPORT_PDR_EPPD7 (0x80) |
| 112 | |
| 113 | /* EPFR */ |
| 114 | #define EPORT_FR_EPF1 (0x02) |
| 115 | #define EPORT_FR_EPF2 (0x04) |
| 116 | #define EPORT_FR_EPF3 (0x08) |
| 117 | #define EPORT_FR_EPF4 (0x10) |
| 118 | #define EPORT_FR_EPF5 (0x20) |
| 119 | #define EPORT_FR_EPF6 (0x40) |
| 120 | #define EPORT_FR_EPF7 (0x80) |
| 121 | |
| 122 | #endif /* __EPORT_H__ */ |