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git01.mediatek.com / filogic / uboot / 3c26c58fbde7f49751528d172e234b44b1f4a8db / . / include / configs / xpedite550x.h
blob: a1710853548087913a825982ec2306500ed4d442 [file] [log] [blame]
John Schmoller9a0709d2010-10-22 00:20:34 -0500[diff] [blame]1/*
2 * Copyright 2010 Extreme Engineering Solutions, Inc.
3 * Copyright 2007-2008 Freescale Semiconductor, Inc.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23/*
24 * xpedite550x board configuration file
25 */
26#ifndef __CONFIG_H
27#define __CONFIG_H
28
29/*
30 * High Level Configuration Options
31 */
32#define CONFIG_BOOKE 1 /* BOOKE */
33#define CONFIG_E500 1 /* BOOKE e500 family */
34#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
35#define CONFIG_P2020 1
36#define CONFIG_XPEDITE550X 1
37#define CONFIG_SYS_BOARD_NAME "XPedite5500"
38#define CONFIG_SYS_FORM_PMC_XMC 1
39#define CONFIG_PRPMC_PCI_ALIAS "pci0" /* Processor PMC interface on pci0 */
40#define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */
41
42#ifndef CONFIG_SYS_TEXT_BASE
43#define CONFIG_SYS_TEXT_BASE 0xfff80000
44#endif
45
46#define CONFIG_PCI 1 /* Enable PCI/PCIE */
47#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
48#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
49#define CONFIG_PCIE1 1 /* PCIE controler 1 (PEX8112 or XMC) */
50#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
Gabor Juhosb4458732013-05-30 07:06:12 +0000[diff] [blame]51#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
John Schmoller9a0709d2010-10-22 00:20:34 -0500[diff] [blame]52#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
53#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
54#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
55#define CONFIG_FSL_ELBC 1
56
57/*
58 * Multicore config
59 */
60#define CONFIG_MP
61#define CONFIG_BPTR_VIRT_ADDR 0xee000000 /* virt boot page address */
62#define CONFIG_MPC8xxx_DISABLE_BPTR /* Don't leave BPTR enabled */
63
64/*
65 * DDR config
66 */
67#define CONFIG_FSL_DDR3
68#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
69#define CONFIG_DDR_SPD
70#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
Kumar Galac68e86c2011-01-31 22:18:47 -0600[diff] [blame]71#define SPD_EEPROM_ADDRESS 0x54
John Schmoller9a0709d2010-10-22 00:20:34 -0500[diff] [blame]72#define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */
73#define CONFIG_NUM_DDR_CONTROLLERS 1
74#define CONFIG_DIMM_SLOTS_PER_CTLR 1
75#define CONFIG_CHIP_SELECTS_PER_CTRL 2
76#define CONFIG_DDR_ECC
77#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
78#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
79#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
80#define CONFIG_VERY_BIG_RAM
81
82#ifndef __ASSEMBLY__
83extern unsigned long get_board_sys_clk(unsigned long dummy);
84extern unsigned long get_board_ddr_clk(unsigned long dummy);
85#endif
86
87#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */
88#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /* ddrclk for MPC85xx */
89
90/*
91 * These can be toggled for performance analysis, otherwise use default.
92 */
93#define CONFIG_L2_CACHE /* toggle L2 cache */
94#define CONFIG_BTB /* toggle branch predition */
95#define CONFIG_ENABLE_36BIT_PHYS 1
96
Timur Tabid8f341c2011-08-04 18:03:41 -0500[diff] [blame]97#define CONFIG_SYS_CCSRBAR 0xef000000
98#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
John Schmoller9a0709d2010-10-22 00:20:34 -0500[diff] [blame]99
100/*
101 * Diagnostics
102 */
103#define CONFIG_SYS_ALT_MEMTEST
104#define CONFIG_SYS_MEMTEST_START 0x10000000
105#define CONFIG_SYS_MEMTEST_END 0x20000000
106#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
107 CONFIG_SYS_POST_I2C)
108#define I2C_ADDR_LIST {CONFIG_SYS_I2C_EEPROM_ADDR, \
109 CONFIG_SYS_I2C_LM75_ADDR, \
110 CONFIG_SYS_I2C_LM90_ADDR, \
111 CONFIG_SYS_I2C_PCA953X_ADDR0, \
112 CONFIG_SYS_I2C_PCA953X_ADDR2, \
113 CONFIG_SYS_I2C_PCA953X_ADDR3, \
114 CONFIG_SYS_I2C_RTC_ADDR}
115
116/*
117 * Memory map
118 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
119 * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable
120 * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
121 * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable
122 * 0xee00_0000 0xee00_ffff Boot page translation 4K non-cacheable
123 * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
124 * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
125 * 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable
126 * 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable
127 */
128
129#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3)
130
131/*
132 * NAND flash configuration
133 */
134#define CONFIG_SYS_NAND_BASE 0xef800000
135#define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */
136#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, \
137 CONFIG_SYS_NAND_BASE2}
138#define CONFIG_SYS_MAX_NAND_DEVICE 2
139#define CONFIG_MTD_NAND_VERIFY_WRITE
140#define CONFIG_SYS_NAND_QUIET_TEST /* 2nd NAND flash not always populated */
141#define CONFIG_NAND_FSL_ELBC
142
143/*
144 * NOR flash configuration
145 */
146#define CONFIG_SYS_FLASH_BASE 0xf8000000
147#define CONFIG_SYS_FLASH_BASE2 0xf0000000
148#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
149#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
150#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
151#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
152#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
153#define CONFIG_FLASH_CFI_DRIVER
154#define CONFIG_SYS_FLASH_CFI
155#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
156#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \
157 {0xf7f40000, 0xc0000} }
158#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
159
160/*
161 * Chip select configuration
162 */
163/* NOR Flash 0 on CS0 */
164#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
165 BR_PS_16 | \
166 BR_V)
167#define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB | \
168 OR_GPCM_CSNT | \
169 OR_GPCM_XACS | \
170 OR_GPCM_ACS_DIV2 | \
171 OR_GPCM_SCY_8 | \
172 OR_GPCM_TRLX | \
173 OR_GPCM_EHTR | \
174 OR_GPCM_EAD)
175
176/* NOR Flash 1 on CS1 */
177#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 | \
178 BR_PS_16 | \
179 BR_V)
180#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
181
182/* NAND flash on CS2 */
183#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE | \
184 (2<<BR_DECC_SHIFT) | \
185 BR_PS_8 | \
186 BR_MS_FCM | \
187 BR_V)
188
189/* NAND flash on CS2 */
190#define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB | \
191 OR_FCM_PGS | \
192 OR_FCM_CSCT | \
193 OR_FCM_CST | \
194 OR_FCM_CHT | \
195 OR_FCM_SCY_1 | \
196 OR_FCM_TRLX | \
197 OR_FCM_EHTR)
198
199/* NAND flash on CS3 */
200#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 | \
201 (2<<BR_DECC_SHIFT) | \
202 BR_PS_8 | \
203 BR_MS_FCM | \
204 BR_V)
205#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
206
207/*
208 * Use L1 as initial stack
209 */
210#define CONFIG_SYS_INIT_RAM_LOCK 1
211#define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200[diff] [blame]212#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
John Schmoller9a0709d2010-10-22 00:20:34 -0500[diff] [blame]213
Wolfgang Denk0191e472010-10-26 14:34:52 +0200[diff] [blame]214#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
John Schmoller9a0709d2010-10-22 00:20:34 -0500[diff] [blame]215#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
216
217#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
218#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
219
220/*
221 * Serial Port
222 */
223#define CONFIG_CONS_INDEX 1
224#define CONFIG_SYS_NS16550
225#define CONFIG_SYS_NS16550_SERIAL
226#define CONFIG_SYS_NS16550_REG_SIZE 1
227#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
228#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
229#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
230#define CONFIG_SYS_BAUDRATE_TABLE \
231 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
232#define CONFIG_BAUDRATE 115200
233#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
234#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
235
236/*
237 * Use the HUSH parser
238 */
239#define CONFIG_SYS_HUSH_PARSER
John Schmoller9a0709d2010-10-22 00:20:34 -0500[diff] [blame]240
241/*
242 * Pass open firmware flat tree
243 */
244#define CONFIG_OF_LIBFDT 1
245#define CONFIG_OF_BOARD_SETUP 1
246#define CONFIG_OF_STDOUT_VIA_ALIAS 1
247#define CONFIG_FDT_FIXUP_PCI_IRQ 1
248
249/*
250 * I2C
251 */
252#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
253#define CONFIG_HARD_I2C /* I2C with hardware support */
254#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
255#define CONFIG_SYS_I2C_SLAVE 0x7F
256#define CONFIG_SYS_I2C_OFFSET 0x3000
257#define CONFIG_SYS_I2C2_OFFSET 0x3100
258#define CONFIG_I2C_MULTI_BUS
259
260/* I2C DS7505 temperature sensor */
261#define CONFIG_DTT_LM75
262#define CONFIG_DTT_SENSORS { 0 }
263#define CONFIG_SYS_I2C_LM75_ADDR 0x48
264
265/* I2C ADT7461 temperature sensor */
266#define CONFIG_SYS_I2C_LM90_ADDR 0x4C
267
268/* I2C EEPROM - AT24C128B */
269#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
270#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
271#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
272#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */
273
274/* I2C RTC */
275#define CONFIG_RTC_M41T11 1
276#define CONFIG_SYS_I2C_RTC_ADDR 0x68
277#define CONFIG_SYS_M41T11_BASE_YEAR 2000
278
279/* GPIO */
280#define CONFIG_PCA953X
281#define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18
282#define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c
283#define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e
284#define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f
285#define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0
286
287/*
288 * GPIO pin definitions, PU = pulled high, PD = pulled low
289 */
290/* PCA9557 @ 0x18*/
291#define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01 /* PU; UART0 enable (1: enabled) */
292#define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02 /* PU; UART0 serial mode select (1: RS-485, 0: RS-232) */
293#define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04 /* PU; UART1 enable (1: enabled) */
294#define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08 /* PU; UART1 serial mode select (1: RS-485, 0: RS-232) */
295#define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10 /* PU; Boot flash CS select */
296#define CONFIG_SYS_PCA953X_NVM_WP 0x20 /* PU; Write protection (0: disabled, 1: enabled) */
297
298/* PCA9557 @ 0x1e*/
299#define CONFIG_SYS_PCA953X_XMC_GA0 0x01 /* PU; */
300#define CONFIG_SYS_PCA953X_XMC_GA1 0x02 /* PU; */
301#define CONFIG_SYS_PCA953X_XMC_GA2 0x04 /* PU; */
302#define CONFIG_SYS_PCA953X_XMC_WAKE 0x10 /* PU; */
303#define CONFIG_SYS_PCA953X_XMC_BIST 0x20 /* Enable XMC BIST */
304#define CONFIG_SYS_PCA953X_PMC_EREADY 0x40 /* PU; PMC PCI eready */
305#define CONFIG_SYS_PCA953X_PMC_MONARCH 0x80 /* PMC monarch mode enable */
306
307/* PCA9557 @ 0x1f */
308#define CONFIG_SYS_PCA953X_MC_GPIO0 0x01 /* PU; */
309#define CONFIG_SYS_PCA953X_MC_GPIO1 0x02 /* PU; */
310#define CONFIG_SYS_PCA953X_MC_GPIO2 0x04 /* PU; */
311#define CONFIG_SYS_PCA953X_MC_GPIO3 0x08 /* PU; */
312#define CONFIG_SYS_PCA953X_MC_GPIO4 0x10 /* PU; */
313#define CONFIG_SYS_PCA953X_MC_GPIO5 0x20 /* PU; */
314#define CONFIG_SYS_PCA953X_MC_GPIO6 0x40 /* PU; */
315#define CONFIG_SYS_PCA953X_MC_GPIO7 0x80 /* PU; */
316
317/*
318 * General PCI
319 * Memory space is mapped 1-1, but I/O space must start from 0.
320 */
321
322/* controller 1 - PEX8112 or XMC, depending on build option */
323#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
324#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
325#define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */
326#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
327#define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000
328#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
329
330
331/*
332 * Networking options
333 */
334#define CONFIG_TSEC_ENET /* tsec ethernet support */
335#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
John Schmoller9a0709d2010-10-22 00:20:34 -0500[diff] [blame]336#define CONFIG_TSEC_TBI
337#define CONFIG_MII 1 /* MII PHY management */
338#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
339#define CONFIG_ETHPRIME "eTSEC2"
340
Kumar Galac1457f92010-12-01 22:55:54 -0600[diff] [blame]341/*
342 * In-band SGMII auto-negotiation between TBI and BCM5482S PHY fails, force
343 * 1000mbps SGMII link
344 */
345#define CONFIG_TSEC_TBICR_SETTINGS ( \
346 TBICR_PHY_RESET \
347 | TBICR_FULL_DUPLEX \
348 | TBICR_SPEED1_SET \
349 )
350
John Schmoller9a0709d2010-10-22 00:20:34 -0500[diff] [blame]351#define CONFIG_TSEC1 1
352#define CONFIG_TSEC1_NAME "eTSEC1"
353#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
354#define TSEC1_PHY_ADDR 1
355#define TSEC1_PHYIDX 0
356#define CONFIG_HAS_ETH0
357
358#define CONFIG_TSEC2 1
359#define CONFIG_TSEC2_NAME "eTSEC2"
360#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
361#define TSEC2_PHY_ADDR 2
362#define TSEC2_PHYIDX 0
363#define CONFIG_HAS_ETH1
364
365#define CONFIG_TSEC3 1
366#define CONFIG_TSEC3_NAME "eTSEC3"
367#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
368#define TSEC3_PHY_ADDR 3
369#define TSEC3_PHYIDX 0
370#define CONFIG_HAS_ETH2
371
372/*
373 * USB
374 */
375#define CONFIG_USB_STORAGE
376#define CONFIG_USB_EHCI
377#define CONFIG_USB_EHCI_FSL
378#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
379#define CONFIG_DOS_PARTITION
380
381/*
382 * Command configuration.
383 */
384#include <config_cmd_default.h>
385
386#define CONFIG_CMD_ASKENV
387#define CONFIG_CMD_DATE
388#define CONFIG_CMD_DHCP
389#define CONFIG_CMD_DTT
390#define CONFIG_CMD_EEPROM
391#define CONFIG_CMD_ELF
392#define CONFIG_CMD_FLASH
393#define CONFIG_CMD_I2C
394#define CONFIG_CMD_JFFS2
395#define CONFIG_CMD_MII
396#define CONFIG_CMD_NAND
397#define CONFIG_CMD_NET
398#define CONFIG_CMD_PCA953X
399#define CONFIG_CMD_PCA953X_INFO
400#define CONFIG_CMD_PCI
401#define CONFIG_CMD_PCI_ENUM
402#define CONFIG_CMD_PING
403#define CONFIG_CMD_REGINFO
404#define CONFIG_CMD_SAVEENV
405#define CONFIG_CMD_SNTP
406#define CONFIG_CMD_USB
407
408/*
409 * Miscellaneous configurable options
410 */
411#define CONFIG_SYS_LONGHELP /* undef to save memory */
412#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
413#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
414#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
415#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
416#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
417#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
418#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
419#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
420#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
421#define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
422#define CONFIG_BOOTDELAY 3 /* -1 disables auto-boot */
423#define CONFIG_PANIC_HANG /* do not reset board on panic */
424#define CONFIG_PREBOOT /* enable preboot variable */
425#define CONFIG_FIT 1
426#define CONFIG_FIT_VERBOSE 1
427#define CONFIG_INTEGRITY /* support booting INTEGRITY OS */
428
429/*
430 * For booting Linux, the board info and command line data
431 * have to be in the first 16 MB of memory, since this is
432 * the maximum mapped by the Linux kernel during initialization.
433 */
434#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
435#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
436
437/*
John Schmoller9a0709d2010-10-22 00:20:34 -0500[diff] [blame]438 * Environment Configuration
439 */
440#define CONFIG_ENV_IS_IN_FLASH 1
441#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */
442#define CONFIG_ENV_SIZE 0x8000
443#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024))
444
445/*
446 * Flash memory map:
447 * fff80000 - ffffffff Pri U-Boot (512 KB)
448 * fff40000 - fff7ffff Pri U-Boot Environment (256 KB)
449 * fff00000 - fff3ffff Pri FDT (256KB)
450 * fef00000 - ffefffff Pri OS image (16MB)
451 * f8000000 - feefffff Pri OS Use/Filesystem (111MB)
452 *
453 * f7f80000 - f7ffffff Sec U-Boot (512 KB)
454 * f7f40000 - f7f7ffff Sec U-Boot Environment (256 KB)
455 * f7f00000 - f7f3ffff Sec FDT (256KB)
456 * f6f00000 - f7efffff Sec OS image (16MB)
457 * f0000000 - f6efffff Sec OS Use/Filesystem (111MB)
458 */
Marek Vasut0b3176c2012-09-23 17:41:24 +0200[diff] [blame]459#define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff80000)
460#define CONFIG_UBOOT2_ENV_ADDR __stringify(0xf7f80000)
461#define CONFIG_FDT1_ENV_ADDR __stringify(0xfff00000)
462#define CONFIG_FDT2_ENV_ADDR __stringify(0xf7f00000)
463#define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000)
464#define CONFIG_OS2_ENV_ADDR __stringify(0xf6f00000)
John Schmoller9a0709d2010-10-22 00:20:34 -0500[diff] [blame]465
466#define CONFIG_PROG_UBOOT1 \
467 "$download_cmd $loadaddr $ubootfile; " \
468 "if test $? -eq 0; then " \
469 "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
470 "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
471 "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \
472 "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
473 "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \
474 "if test $? -ne 0; then " \
475 "echo PROGRAM FAILED; " \
476 "else; " \
477 "echo PROGRAM SUCCEEDED; " \
478 "fi; " \
479 "else; " \
480 "echo DOWNLOAD FAILED; " \
481 "fi;"
482
483#define CONFIG_PROG_UBOOT2 \
484 "$download_cmd $loadaddr $ubootfile; " \
485 "if test $? -eq 0; then " \
486 "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
487 "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
488 "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \
489 "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
490 "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \
491 "if test $? -ne 0; then " \
492 "echo PROGRAM FAILED; " \
493 "else; " \
494 "echo PROGRAM SUCCEEDED; " \
495 "fi; " \
496 "else; " \
497 "echo DOWNLOAD FAILED; " \
498 "fi;"
499
500#define CONFIG_BOOT_OS_NET \
501 "$download_cmd $osaddr $osfile; " \
502 "if test $? -eq 0; then " \
503 "if test -n $fdtaddr; then " \
504 "$download_cmd $fdtaddr $fdtfile; " \
505 "if test $? -eq 0; then " \
506 "bootm $osaddr - $fdtaddr; " \
507 "else; " \
508 "echo FDT DOWNLOAD FAILED; " \
509 "fi; " \
510 "else; " \
511 "bootm $osaddr; " \
512 "fi; " \
513 "else; " \
514 "echo OS DOWNLOAD FAILED; " \
515 "fi;"
516
517#define CONFIG_PROG_OS1 \
518 "$download_cmd $osaddr $osfile; " \
519 "if test $? -eq 0; then " \
520 "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \
521 "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
522 "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
523 "if test $? -ne 0; then " \
524 "echo OS PROGRAM FAILED; " \
525 "else; " \
526 "echo OS PROGRAM SUCCEEDED; " \
527 "fi; " \
528 "else; " \
529 "echo OS DOWNLOAD FAILED; " \
530 "fi;"
531
532#define CONFIG_PROG_OS2 \
533 "$download_cmd $osaddr $osfile; " \
534 "if test $? -eq 0; then " \
535 "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \
536 "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
537 "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
538 "if test $? -ne 0; then " \
539 "echo OS PROGRAM FAILED; " \
540 "else; " \
541 "echo OS PROGRAM SUCCEEDED; " \
542 "fi; " \
543 "else; " \
544 "echo OS DOWNLOAD FAILED; " \
545 "fi;"
546
547#define CONFIG_PROG_FDT1 \
548 "$download_cmd $fdtaddr $fdtfile; " \
549 "if test $? -eq 0; then " \
550 "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \
551 "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
552 "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
553 "if test $? -ne 0; then " \
554 "echo FDT PROGRAM FAILED; " \
555 "else; " \
556 "echo FDT PROGRAM SUCCEEDED; " \
557 "fi; " \
558 "else; " \
559 "echo FDT DOWNLOAD FAILED; " \
560 "fi;"
561
562#define CONFIG_PROG_FDT2 \
563 "$download_cmd $fdtaddr $fdtfile; " \
564 "if test $? -eq 0; then " \
565 "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \
566 "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
567 "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
568 "if test $? -ne 0; then " \
569 "echo FDT PROGRAM FAILED; " \
570 "else; " \
571 "echo FDT PROGRAM SUCCEEDED; " \
572 "fi; " \
573 "else; " \
574 "echo FDT DOWNLOAD FAILED; " \
575 "fi;"
576
577#define CONFIG_EXTRA_ENV_SETTINGS \
578 "autoload=yes\0" \
579 "download_cmd=tftp\0" \
580 "console_args=console=ttyS0,115200\0" \
581 "root_args=root=/dev/nfs rw\0" \
582 "misc_args=ip=on\0" \
583 "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
584 "bootfile=/home/user/file\0" \
585 "osfile=/home/user/board.uImage\0" \
586 "fdtfile=/home/user/board.dtb\0" \
587 "ubootfile=/home/user/u-boot.bin\0" \
588 "fdtaddr=c00000\0" \
589 "osaddr=0x1000000\0" \
590 "loadaddr=0x1000000\0" \
591 "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \
592 "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \
593 "prog_os1="CONFIG_PROG_OS1"\0" \
594 "prog_os2="CONFIG_PROG_OS2"\0" \
595 "prog_fdt1="CONFIG_PROG_FDT1"\0" \
596 "prog_fdt2="CONFIG_PROG_FDT2"\0" \
597 "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \
598 "bootcmd_flash1=run set_bootargs; " \
599 "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
600 "bootcmd_flash2=run set_bootargs; " \
601 "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
602 "bootcmd=run bootcmd_flash1\0"
603#endif /* __CONFIG_H */