Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 3c1b9f1b0a45653bf1e1f41d736dbe03dae308ab / . / arch / arm / dts / at91sam9rl.dtsi
blob: 8249994878d747bfb53c7473d09f3752c9617739 [file] [log] [blame]
Wenyou Yang59aebeb2017-04-18 13:49:38 +0800[diff] [blame]1/*
2 * at91sam9rl.dtsi - Device Tree Include file for AT91SAM9RL family SoC
3 *
4 * Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com>
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#include "skeleton.dtsi"
10#include <dt-bindings/pinctrl/at91.h>
11#include <dt-bindings/clock/at91.h>
12#include <dt-bindings/interrupt-controller/irq.h>
13#include <dt-bindings/gpio/gpio.h>
14#include <dt-bindings/pwm/pwm.h>
15
16/ {
17 model = "Atmel AT91SAM9RL family SoC";
18 compatible = "atmel,at91sam9rl", "atmel,at91sam9";
19 interrupt-parent = <&aic>;
20
21 aliases {
22 serial0 = &dbgu;
23 serial1 = &usart0;
24 serial2 = &usart1;
25 serial3 = &usart2;
26 serial4 = &usart3;
27 gpio0 = &pioA;
28 gpio1 = &pioB;
29 gpio2 = &pioC;
30 gpio3 = &pioD;
31 tcb0 = &tcb0;
32 i2c0 = &i2c0;
33 i2c1 = &i2c1;
34 ssc0 = &ssc0;
35 ssc1 = &ssc1;
36 pwm0 = &pwm0;
37 };
38
39 cpus {
40 #address-cells = <0>;
41 #size-cells = <0>;
42
43 cpu {
44 compatible = "arm,arm926ej-s";
45 device_type = "cpu";
46 };
47 };
48
49 memory {
50 reg = <0x20000000 0x04000000>;
51 };
52
53 clocks {
54 slow_xtal: slow_xtal {
55 compatible = "fixed-clock";
56 #clock-cells = <0>;
57 clock-frequency = <0>;
58 };
59
60 main_xtal: main_xtal {
61 compatible = "fixed-clock";
62 #clock-cells = <0>;
63 clock-frequency = <0>;
64 };
65
66 adc_op_clk: adc_op_clk{
67 compatible = "fixed-clock";
68 #clock-cells = <0>;
69 clock-frequency = <1000000>;
70 };
71 };
72
73 sram: sram@00300000 {
74 compatible = "mmio-sram";
75 reg = <0x00300000 0x10000>;
76 };
77
78 ahb {
79 compatible = "simple-bus";
80 #address-cells = <1>;
81 #size-cells = <1>;
82 ranges;
83 u-boot,dm-pre-reloc;
84
85 fb0: fb@00500000 {
86 compatible = "atmel,at91sam9rl-lcdc";
87 reg = <0x00500000 0x1000>;
88 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 3>;
89 pinctrl-names = "default";
90 pinctrl-0 = <&pinctrl_fb>;
91 clocks = <&lcd_clk>, <&lcd_clk>;
92 clock-names = "hclk", "lcdc_clk";
93 status = "disabled";
94 };
95
96 nand0: nand@40000000 {
97 compatible = "atmel,at91rm9200-nand";
98 #address-cells = <1>;
99 #size-cells = <1>;
100 reg = <0x40000000 0x10000000>,
101 <0xffffe800 0x200>;
102 atmel,nand-addr-offset = <21>;
103 atmel,nand-cmd-offset = <22>;
104 atmel,nand-has-dma;
105 pinctrl-names = "default";
106 pinctrl-0 = <&pinctrl_nand>;
107 gpios = <&pioD 17 GPIO_ACTIVE_HIGH>,
108 <&pioB 6 GPIO_ACTIVE_HIGH>,
109 <0>;
110 status = "disabled";
111 };
112
113 apb {
114 compatible = "simple-bus";
115 #address-cells = <1>;
116 #size-cells = <1>;
117 ranges;
118 u-boot,dm-pre-reloc;
119
120 tcb0: timer@fffa0000 {
121 compatible = "atmel,at91rm9200-tcb";
122 reg = <0xfffa0000 0x100>;
123 interrupts = <16 IRQ_TYPE_LEVEL_HIGH 0>,
124 <17 IRQ_TYPE_LEVEL_HIGH 0>,
125 <18 IRQ_TYPE_LEVEL_HIGH 0>;
126 clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>, <&clk32k>;
127 clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
128 };
129
130 mmc0: mmc@fffa4000 {
131 compatible = "atmel,hsmci";
132 reg = <0xfffa4000 0x600>;
133 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>;
134 #address-cells = <1>;
135 #size-cells = <0>;
136 pinctrl-names = "default";
137 clocks = <&mci0_clk>;
138 clock-names = "mci_clk";
139 status = "disabled";
140 };
141
142 i2c0: i2c@fffa8000 {
143 compatible = "atmel,at91sam9260-i2c";
144 reg = <0xfffa8000 0x100>;
145 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>;
146 #address-cells = <1>;
147 #size-cells = <0>;
148 clocks = <&twi0_clk>;
149 status = "disabled";
150 };
151
152 i2c1: i2c@fffac000 {
153 compatible = "atmel,at91sam9260-i2c";
154 reg = <0xfffac000 0x100>;
155 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>;
156 #address-cells = <1>;
157 #size-cells = <0>;
158 status = "disabled";
159 };
160
161 usart0: serial@fffb0000 {
162 compatible = "atmel,at91sam9260-usart";
163 reg = <0xfffb0000 0x200>;
164 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
165 atmel,use-dma-rx;
166 atmel,use-dma-tx;
167 pinctrl-names = "default";
168 pinctrl-0 = <&pinctrl_usart0>;
169 clocks = <&usart0_clk>;
170 clock-names = "usart";
171 status = "disabled";
172 };
173
174 usart1: serial@fffb4000 {
175 compatible = "atmel,at91sam9260-usart";
176 reg = <0xfffb4000 0x200>;
177 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
178 atmel,use-dma-rx;
179 atmel,use-dma-tx;
180 pinctrl-names = "default";
181 pinctrl-0 = <&pinctrl_usart1>;
182 clocks = <&usart1_clk>;
183 clock-names = "usart";
184 status = "disabled";
185 };
186
187 usart2: serial@fffb8000 {
188 compatible = "atmel,at91sam9260-usart";
189 reg = <0xfffb8000 0x200>;
190 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
191 atmel,use-dma-rx;
192 atmel,use-dma-tx;
193 pinctrl-names = "default";
194 pinctrl-0 = <&pinctrl_usart2>;
195 clocks = <&usart2_clk>;
196 clock-names = "usart";
197 status = "disabled";
198 };
199
200 usart3: serial@fffbc000 {
201 compatible = "atmel,at91sam9260-usart";
202 reg = <0xfffbc000 0x200>;
203 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 5>;
204 atmel,use-dma-rx;
205 atmel,use-dma-tx;
206 pinctrl-names = "default";
207 pinctrl-0 = <&pinctrl_usart3>;
208 clocks = <&usart3_clk>;
209 clock-names = "usart";
210 status = "disabled";
211 };
212
213 ssc0: ssc@fffc0000 {
214 compatible = "atmel,at91sam9rl-ssc";
215 reg = <0xfffc0000 0x4000>;
216 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
217 pinctrl-names = "default";
218 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
219 status = "disabled";
220 };
221
222 ssc1: ssc@fffc4000 {
223 compatible = "atmel,at91sam9rl-ssc";
224 reg = <0xfffc4000 0x4000>;
225 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
226 pinctrl-names = "default";
227 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
228 status = "disabled";
229 };
230
231 pwm0: pwm@fffc8000 {
232 compatible = "atmel,at91sam9rl-pwm";
233 reg = <0xfffc8000 0x300>;
234 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 4>;
235 #pwm-cells = <3>;
236 clocks = <&pwm_clk>;
237 clock-names = "pwm_clk";
238 status = "disabled";
239 };
240
241 spi0: spi@fffcc000 {
242 #address-cells = <1>;
243 #size-cells = <0>;
244 compatible = "atmel,at91rm9200-spi";
245 reg = <0xfffcc000 0x200>;
246 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
247 pinctrl-names = "default";
248 pinctrl-0 = <&pinctrl_spi0>;
249 clocks = <&spi0_clk>;
250 clock-names = "spi_clk";
251 status = "disabled";
252 };
253
254 adc0: adc@fffd0000 {
255 #address-cells = <1>;
256 #size-cells = <0>;
257 compatible = "atmel,at91sam9rl-adc";
258 reg = <0xfffd0000 0x100>;
259 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
260 clocks = <&adc_clk>, <&adc_op_clk>;
261 clock-names = "adc_clk", "adc_op_clk";
262 atmel,adc-use-external-triggers;
263 atmel,adc-channels-used = <0x3f>;
264 atmel,adc-vref = <3300>;
265 atmel,adc-startup-time = <40>;
266 atmel,adc-res = <8 10>;
267 atmel,adc-res-names = "lowres", "highres";
268 atmel,adc-use-res = "highres";
269
270 trigger0 {
271 trigger-name = "timer-counter-0";
272 trigger-value = <0x1>;
273 };
274 trigger1 {
275 trigger-name = "timer-counter-1";
276 trigger-value = <0x3>;
277 };
278
279 trigger2 {
280 trigger-name = "timer-counter-2";
281 trigger-value = <0x5>;
282 };
283
284 trigger3 {
285 trigger-name = "external";
286 trigger-value = <0x13>;
287 trigger-external;
288 };
289 };
290
291 usb0: gadget@fffd4000 {
292 #address-cells = <1>;
293 #size-cells = <0>;
294 compatible = "atmel,at91sam9rl-udc";
295 reg = <0x00600000 0x100000>,
296 <0xfffd4000 0x4000>;
297 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
298 clocks = <&udphs_clk>, <&utmi>;
299 clock-names = "pclk", "hclk";
300 status = "disabled";
301
302 ep@0 {
303 reg = <0>;
304 atmel,fifo-size = <64>;
305 atmel,nb-banks = <1>;
306 };
307
308 ep@1 {
309 reg = <1>;
310 atmel,fifo-size = <1024>;
311 atmel,nb-banks = <2>;
312 atmel,can-dma;
313 atmel,can-isoc;
314 };
315
316 ep@2 {
317 reg = <2>;
318 atmel,fifo-size = <1024>;
319 atmel,nb-banks = <2>;
320 atmel,can-dma;
321 atmel,can-isoc;
322 };
323
324 ep@3 {
325 reg = <3>;
326 atmel,fifo-size = <1024>;
327 atmel,nb-banks = <3>;
328 atmel,can-dma;
329 };
330
331 ep@4 {
332 reg = <4>;
333 atmel,fifo-size = <1024>;
334 atmel,nb-banks = <3>;
335 atmel,can-dma;
336 };
337
338 ep@5 {
339 reg = <5>;
340 atmel,fifo-size = <1024>;
341 atmel,nb-banks = <3>;
342 atmel,can-dma;
343 atmel,can-isoc;
344 };
345
346 ep@6 {
347 reg = <6>;
348 atmel,fifo-size = <1024>;
349 atmel,nb-banks = <3>;
350 atmel,can-dma;
351 atmel,can-isoc;
352 };
353 };
354
355 dma0: dma-controller@ffffe600 {
356 compatible = "atmel,at91sam9rl-dma";
357 reg = <0xffffe600 0x200>;
358 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
359 #dma-cells = <2>;
360 clocks = <&dma0_clk>;
361 clock-names = "dma_clk";
362 };
363
364 ramc0: ramc@ffffea00 {
365 compatible = "atmel,at91sam9260-sdramc";
366 reg = <0xffffea00 0x200>;
367 };
368
369 aic: interrupt-controller@fffff000 {
370 #interrupt-cells = <3>;
371 compatible = "atmel,at91rm9200-aic";
372 interrupt-controller;
373 reg = <0xfffff000 0x200>;
374 atmel,external-irqs = <31>;
375 };
376
377 dbgu: serial@fffff200 {
378 compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
379 reg = <0xfffff200 0x200>;
380 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
381 pinctrl-names = "default";
382 pinctrl-0 = <&pinctrl_dbgu>;
383 clocks = <&mck>;
384 clock-names = "usart";
385 status = "disabled";
386 };
387
388 pinctrl@fffff400 {
389 #address-cells = <1>;
390 #size-cells = <1>;
391 compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
392 ranges = <0xfffff400 0xfffff400 0x800>;
393 reg = <0xfffff400 0x200
394 0xfffff600 0x200
395 0xfffff800 0x200
396 0xfffffa00 0x200
397 >;
398
399 atmel,mux-mask =
400 /* A B */
401 <0xffffffff 0xe05c6738>, /* pioA */
402 <0xffffffff 0x0000c780>, /* pioB */
403 <0xffffffff 0xe3ffff0e>, /* pioC */
404 <0x003fffff 0x0001ff3c>; /* pioD */
405 u-boot,dm-pre-reloc;
406
407 /* shared pinctrl settings */
408 adc0 {
409 pinctrl_adc0_ts: adc0_ts-0 {
410 atmel,pins =
411 <AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE>,
412 <AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE>,
413 <AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE>,
414 <AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE>;
415 };
416
417 pinctrl_adc0_ad0: adc0_ad0-0 {
418 atmel,pins = <AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE>;
419 };
420
421 pinctrl_adc0_ad1: adc0_ad1-0 {
422 atmel,pins = <AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE>;
423 };
424
425 pinctrl_adc0_ad2: adc0_ad2-0 {
426 atmel,pins = <AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE>;
427 };
428
429 pinctrl_adc0_ad3: adc0_ad3-0 {
430 atmel,pins = <AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE>;
431 };
432
433 pinctrl_adc0_ad4: adc0_ad4-0 {
434 atmel,pins = <AT91_PIOD 6 AT91_PERIPH_A AT91_PINCTRL_NONE>;
435 };
436
437 pinctrl_adc0_ad5: adc0_ad5-0 {
438 atmel,pins = <AT91_PIOD 7 AT91_PERIPH_A AT91_PINCTRL_NONE>;
439 };
440
441 pinctrl_adc0_adtrg: adc0_adtrg-0 {
442 atmel,pins = <AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;
443 };
444 };
445
446 dbgu {
447 u-boot,dm-pre-reloc;
448 pinctrl_dbgu: dbgu-0 {
449 atmel,pins =
450 <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
451 <AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE>;
452 };
453 };
454
455 fb {
456 pinctrl_fb: fb-0 {
457 atmel,pins =
458 <AT91_PIOC 1 AT91_PERIPH_B AT91_PINCTRL_NONE>,
459 <AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE>,
460 <AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE>,
461 <AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE>,
462 <AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE>,
463 <AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_NONE>,
464 <AT91_PIOC 10 AT91_PERIPH_B AT91_PINCTRL_NONE>,
465 <AT91_PIOC 11 AT91_PERIPH_B AT91_PINCTRL_NONE>,
466 <AT91_PIOC 12 AT91_PERIPH_B AT91_PINCTRL_NONE>,
467 <AT91_PIOC 13 AT91_PERIPH_B AT91_PINCTRL_NONE>,
468 <AT91_PIOC 15 AT91_PERIPH_B AT91_PINCTRL_NONE>,
469 <AT91_PIOC 16 AT91_PERIPH_B AT91_PINCTRL_NONE>,
470 <AT91_PIOC 17 AT91_PERIPH_B AT91_PINCTRL_NONE>,
471 <AT91_PIOC 18 AT91_PERIPH_B AT91_PINCTRL_NONE>,
472 <AT91_PIOC 19 AT91_PERIPH_B AT91_PINCTRL_NONE>,
473 <AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE>,
474 <AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE>,
475 <AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE>,
476 <AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>,
477 <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE>,
478 <AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>;
479 };
480 };
481
482 i2c_gpio0 {
483 pinctrl_i2c_gpio0: i2c_gpio0-0 {
484 atmel,pins =
485 <AT91_PIOA 23 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>,
486 <AT91_PIOA 24 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>;
487 };
488 };
489
490 i2c_gpio1 {
491 pinctrl_i2c_gpio1: i2c_gpio1-0 {
492 atmel,pins =
493 <AT91_PIOD 10 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>,
494 <AT91_PIOD 11 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>;
495 };
496 };
497
498 mmc0 {
499 pinctrl_mmc0_clk: mmc0_clk-0 {
500 atmel,pins =
501 <AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>;
502 };
503
504 pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 {
505 atmel,pins =
506 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
507 <AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
508 };
509
510 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
511 atmel,pins =
512 <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
513 <AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
514 <AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
515 };
516 };
517
518 nand {
519 pinctrl_nand: nand-0 {
520 atmel,pins =
521 <AT91_PIOD 17 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>,
522 <AT91_PIOB 6 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
523 };
524
525 pinctrl_nand0_ale_cle: nand_ale_cle-0 {
526 atmel,pins =
527 <AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE>,
528 <AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE>;
529 };
530
531 pinctrl_nand0_oe_we: nand_oe_we-0 {
532 atmel,pins =
533 <AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE>,
534 <AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE>;
535 };
536
537 pinctrl_nand0_cs: nand_cs-0 {
538 atmel,pins =
539 <AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE>;
540 };
541 };
542
543 pwm0 {
544 pinctrl_pwm0_pwm0_0: pwm0_pwm0-0 {
545 atmel,pins = <AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE>;
546 };
547
548 pinctrl_pwm0_pwm0_1: pwm0_pwm0-1 {
549 atmel,pins = <AT91_PIOC 2 AT91_PERIPH_B AT91_PINCTRL_NONE>;
550 };
551
552 pinctrl_pwm0_pwm0_2: pwm0_pwm0-2 {
553 atmel,pins = <AT91_PIOD 14 AT91_PERIPH_B AT91_PINCTRL_NONE>;
554 };
555
556 pinctrl_pwm0_pwm1_0: pwm0_pwm1-0 {
557 atmel,pins = <AT91_PIOB 9 AT91_PERIPH_B AT91_PINCTRL_NONE>;
558 };
559
560 pinctrl_pwm0_pwm1_1: pwm0_pwm1-1 {
561 atmel,pins = <AT91_PIOC 3 AT91_PERIPH_B AT91_PINCTRL_NONE>;
562 };
563
564 pinctrl_pwm0_pwm1_2: pwm0_pwm1-2 {
565 atmel,pins = <AT91_PIOD 15 AT91_PERIPH_B AT91_PINCTRL_NONE>;
566 };
567
568 pinctrl_pwm0_pwm2_0: pwm0_pwm2-0 {
569 atmel,pins = <AT91_PIOD 5 AT91_PERIPH_B AT91_PINCTRL_NONE>;
570 };
571
572 pinctrl_pwm0_pwm2_1: pwm0_pwm2-1 {
573 atmel,pins = <AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE>;
574 };
575
576 pinctrl_pwm0_pwm2_2: pwm0_pwm2-2 {
577 atmel,pins = <AT91_PIOD 16 AT91_PERIPH_B AT91_PINCTRL_NONE>;
578 };
579
580 pinctrl_pwm0_pwm3_0: pwm0_pwm3-0 {
581 atmel,pins = <AT91_PIOD 8 AT91_PERIPH_B AT91_PINCTRL_NONE>;
582 };
583
584 pinctrl_pwm0_pwm3_1: pwm0_pwm3-1 {
585 atmel,pins = <AT91_PIOD 18 AT91_PERIPH_A AT91_PINCTRL_NONE>;
586 };
587 };
588
589 spi0 {
590 pinctrl_spi0: spi0-0 {
591 atmel,pins =
592 <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE>,
593 <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE>,
594 <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
595 };
596 };
597
598 ssc0 {
599 pinctrl_ssc0_tx: ssc0_tx-0 {
600 atmel,pins =
601 <AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE>,
602 <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE>,
603 <AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE>;
604 };
605
606 pinctrl_ssc0_rx: ssc0_rx-0 {
607 atmel,pins =
608 <AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_NONE>,
609 <AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE>,
610 <AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE>;
611 };
612 };
613
614 ssc1 {
615 pinctrl_ssc1_tx: ssc1_tx-0 {
616 atmel,pins =
617 <AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_NONE>,
618 <AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>,
619 <AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE>;
620 };
621
622 pinctrl_ssc1_rx: ssc1_rx-0 {
623 atmel,pins =
624 <AT91_PIOA 8 AT91_PERIPH_B AT91_PINCTRL_NONE>,
625 <AT91_PIOA 9 AT91_PERIPH_B AT91_PINCTRL_NONE>,
626 <AT91_PIOA 14 AT91_PERIPH_B AT91_PINCTRL_NONE>;
627 };
628 };
629
630 tcb0 {
631 pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
632 atmel,pins = <AT91_PIOA 3 AT91_PERIPH_B AT91_PINCTRL_NONE>;
633 };
634
635 pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
636 atmel,pins = <AT91_PIOC 31 AT91_PERIPH_B AT91_PINCTRL_NONE>;
637 };
638
639 pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
640 atmel,pins = <AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>;
641 };
642
643 pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
644 atmel,pins = <AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_NONE>;
645 };
646
647 pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
648 atmel,pins = <AT91_PIOC 29 AT91_PERIPH_B AT91_PINCTRL_NONE>;
649 };
650
651 pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
652 atmel,pins = <AT91_PIOD 10 AT91_PERIPH_B AT91_PINCTRL_NONE>;
653 };
654
655 pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
656 atmel,pins = <AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_NONE>;
657 };
658
659 pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
660 atmel,pins = <AT91_PIOC 30 AT91_PERIPH_B AT91_PINCTRL_NONE>;
661 };
662
663 pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
664 atmel,pins = <AT91_PIOD 11 AT91_PERIPH_B AT91_PINCTRL_NONE>;
665 };
666 };
667
668 usart0 {
669 pinctrl_usart0: usart0-0 {
670 atmel,pins =
671 <AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE>,
672 <AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
673 };
674
675 pinctrl_usart0_rts: usart0_rts-0 {
676 atmel,pins =
677 <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE>;
678 };
679
680 pinctrl_usart0_cts: usart0_cts-0 {
681 atmel,pins =
682 <AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;
683 };
684
685 pinctrl_usart0_dtr_dsr: usart0_dtr_dsr-0 {
686 atmel,pins =
687 <AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE>,
688 <AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;
689 };
690
691 pinctrl_usart0_dcd: usart0_dcd-0 {
692 atmel,pins =
693 <AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE>;
694 };
695
696 pinctrl_usart0_ri: usart0_ri-0 {
697 atmel,pins =
698 <AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE>;
699 };
700
701 pinctrl_usart0_sck: usart0_sck-0 {
702 atmel,pins =
703 <AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE>;
704 };
705 };
706
707 usart1 {
708 pinctrl_usart1: usart1-0 {
709 atmel,pins =
710 <AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
711 <AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE>;
712 };
713
714 pinctrl_usart1_rts: usart1_rts-0 {
715 atmel,pins =
716 <AT91_PIOA 18 AT91_PERIPH_B AT91_PINCTRL_NONE>;
717 };
718
719 pinctrl_usart1_cts: usart1_cts-0 {
720 atmel,pins =
721 <AT91_PIOA 19 AT91_PERIPH_B AT91_PINCTRL_NONE>;
722 };
723
724 pinctrl_usart1_sck: usart1_sck-0 {
725 atmel,pins =
726 <AT91_PIOD 2 AT91_PERIPH_B AT91_PINCTRL_NONE>;
727 };
728 };
729
730 usart2 {
731 pinctrl_usart2: usart2-0 {
732 atmel,pins =
733 <AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
734 <AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE>;
735 };
736
737 pinctrl_usart2_rts: usart2_rts-0 {
738 atmel,pins =
739 <AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
740 };
741
742 pinctrl_usart2_cts: usart2_cts-0 {
743 atmel,pins =
744 <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE>;
745 };
746
747 pinctrl_usart2_sck: usart2_sck-0 {
748 atmel,pins =
749 <AT91_PIOD 9 AT91_PERIPH_A AT91_PINCTRL_NONE>;
750 };
751 };
752
753 usart3 {
754 pinctrl_usart3: usart3-0 {
755 atmel,pins =
756 <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
757 <AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE>;
758 };
759
760 pinctrl_usart3_rts: usart3_rts-0 {
761 atmel,pins =
762 <AT91_PIOD 4 AT91_PERIPH_B AT91_PINCTRL_NONE>;
763 };
764
765 pinctrl_usart3_cts: usart3_cts-0 {
766 atmel,pins =
767 <AT91_PIOD 3 AT91_PERIPH_B AT91_PINCTRL_NONE>;
768 };
769
770 pinctrl_usart3_sck: usart3_sck-0 {
771 atmel,pins =
772 <AT91_PIOA 20 AT91_PERIPH_B AT91_PINCTRL_NONE>;
773 };
774 };
775 };
776
777 pioA: gpio@fffff400 {
778 compatible = "atmel,at91rm9200-gpio";
779 reg = <0xfffff400 0x200>;
780 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
781 #gpio-cells = <2>;
782 gpio-controller;
783 interrupt-controller;
784 #interrupt-cells = <2>;
785 clocks = <&pioA_clk>;
786 u-boot,dm-pre-reloc;
787 };
788
789 pioB: gpio@fffff600 {
790 compatible = "atmel,at91rm9200-gpio";
791 reg = <0xfffff600 0x200>;
792 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
793 #gpio-cells = <2>;
794 gpio-controller;
795 interrupt-controller;
796 #interrupt-cells = <2>;
797 clocks = <&pioB_clk>;
798 u-boot,dm-pre-reloc;
799 };
800
801 pioC: gpio@fffff800 {
802 compatible = "atmel,at91rm9200-gpio";
803 reg = <0xfffff800 0x200>;
804 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
805 #gpio-cells = <2>;
806 gpio-controller;
807 interrupt-controller;
808 #interrupt-cells = <2>;
809 clocks = <&pioC_clk>;
810 u-boot,dm-pre-reloc;
811 };
812
813 pioD: gpio@fffffa00 {
814 compatible = "atmel,at91rm9200-gpio";
815 reg = <0xfffffa00 0x200>;
816 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
817 #gpio-cells = <2>;
818 gpio-controller;
819 interrupt-controller;
820 #interrupt-cells = <2>;
821 clocks = <&pioD_clk>;
822 u-boot,dm-pre-reloc;
823 };
824
825 pmc: pmc@fffffc00 {
826 compatible = "atmel,at91sam9g45-pmc", "syscon";
827 reg = <0xfffffc00 0x100>;
828 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
829 interrupt-controller;
830 #address-cells = <1>;
831 #size-cells = <0>;
832 #interrupt-cells = <1>;
833 u-boot,dm-pre-reloc;
834
835 main: mainck {
836 compatible = "atmel,at91rm9200-clk-main";
837 #clock-cells = <0>;
838 interrupts-extended = <&pmc AT91_PMC_MOSCS>;
839 clocks = <&main_xtal>;
840 };
841
842 plla: pllack@0 {
843 compatible = "atmel,at91rm9200-clk-pll";
844 #clock-cells = <0>;
845 interrupts-extended = <&pmc AT91_PMC_LOCKA>;
846 clocks = <&main>;
847 reg = <0>;
848 atmel,clk-input-range = <1000000 32000000>;
849 #atmel,pll-clk-output-range-cells = <3>;
850 atmel,pll-clk-output-ranges = <80000000 200000000 0>,
851 <190000000 240000000 2>;
852 };
853
854 utmi: utmick {
855 compatible = "atmel,at91sam9x5-clk-utmi";
856 #clock-cells = <0>;
857 interrupt-parent = <&pmc>;
858 interrupts = <AT91_PMC_LOCKU>;
859 clocks = <&main>;
860 };
861
862 mck: masterck {
863 compatible = "atmel,at91rm9200-clk-master";
864 #clock-cells = <0>;
865 interrupts-extended = <&pmc AT91_PMC_MCKRDY>;
866 clocks = <&clk32k>, <&main>, <&plla>, <&utmi>;
867 atmel,clk-output-range = <0 94000000>;
868 atmel,clk-divisors = <1 2 4 0>;
869 u-boot,dm-pre-reloc;
870 };
871
872 prog: progck {
873 compatible = "atmel,at91rm9200-clk-programmable";
874 #address-cells = <1>;
875 #size-cells = <0>;
876 interrupt-parent = <&pmc>;
877 clocks = <&clk32k>, <&main>, <&plla>, <&utmi>, <&mck>;
878
879 prog0: prog@0 {
880 #clock-cells = <0>;
881 reg = <0>;
882 interrupts = <AT91_PMC_PCKRDY(0)>;
883 };
884
885 prog1: prog@1 {
886 #clock-cells = <0>;
887 reg = <1>;
888 interrupts = <AT91_PMC_PCKRDY(1)>;
889 };
890 };
891
892 systemck {
893 compatible = "atmel,at91rm9200-clk-system";
894 #address-cells = <1>;
895 #size-cells = <0>;
896
897 pck0: pck0@8 {
898 #clock-cells = <0>;
899 reg = <8>;
900 clocks = <&prog0>;
901 };
902
903 pck1: pck1@9 {
904 #clock-cells = <0>;
905 reg = <9>;
906 clocks = <&prog1>;
907 };
908
909 };
910
911 periphck {
912 compatible = "atmel,at91rm9200-clk-peripheral";
913 #address-cells = <1>;
914 #size-cells = <0>;
915 clocks = <&mck>;
916 u-boot,dm-pre-reloc;
917
918 pioA_clk: pioA_clk@2 {
919 #clock-cells = <0>;
920 reg = <2>;
921 u-boot,dm-pre-reloc;
922 };
923
924 pioB_clk: pioB_clk@3 {
925 #clock-cells = <0>;
926 reg = <3>;
927 u-boot,dm-pre-reloc;
928 };
929
930 pioC_clk: pioC_clk@4 {
931 #clock-cells = <0>;
932 reg = <4>;
933 u-boot,dm-pre-reloc;
934 };
935
936 pioD_clk: pioD_clk@5 {
937 #clock-cells = <0>;
938 reg = <5>;
939 u-boot,dm-pre-reloc;
940 };
941
942 usart0_clk: usart0_clk@6 {
943 #clock-cells = <0>;
944 reg = <6>;
945 };
946
947 usart1_clk: usart1_clk@7 {
948 #clock-cells = <0>;
949 reg = <7>;
950 };
951
952 usart2_clk: usart2_clk@8 {
953 #clock-cells = <0>;
954 reg = <8>;
955 };
956
957 usart3_clk: usart3_clk@9 {
958 #clock-cells = <0>;
959 reg = <9>;
960 };
961
962 mci0_clk: mci0_clk@10 {
963 #clock-cells = <0>;
964 reg = <10>;
965 };
966
967 twi0_clk: twi0_clk@11 {
968 #clock-cells = <0>;
969 reg = <11>;
970 };
971
972 twi1_clk: twi1_clk@12 {
973 #clock-cells = <0>;
974 reg = <12>;
975 };
976
977 spi0_clk: spi0_clk@13 {
978 #clock-cells = <0>;
979 reg = <13>;
980 };
981
982 ssc0_clk: ssc0_clk@14 {
983 #clock-cells = <0>;
984 reg = <14>;
985 };
986
987 ssc1_clk: ssc1_clk@15 {
988 #clock-cells = <0>;
989 reg = <15>;
990 };
991
992 tc0_clk: tc0_clk@16 {
993 #clock-cells = <0>;
994 reg = <16>;
995 };
996
997 tc1_clk: tc1_clk@17 {
998 #clock-cells = <0>;
999 reg = <17>;
1000 };
1001
1002 tc2_clk: tc2_clk@18 {
1003 #clock-cells = <0>;
1004 reg = <18>;
1005 };
1006
1007 pwm_clk: pwm_clk@19 {
1008 #clock-cells = <0>;
1009 reg = <19>;
1010 };
1011
1012 adc_clk: adc_clk@20 {
1013 #clock-cells = <0>;
1014 reg = <20>;
1015 };
1016
1017 dma0_clk: dma0_clk@21 {
1018 #clock-cells = <0>;
1019 reg = <21>;
1020 };
1021
1022 udphs_clk: udphs_clk@22 {
1023 #clock-cells = <0>;
1024 reg = <22>;
1025 };
1026
1027 lcd_clk: lcd_clk@23 {
1028 #clock-cells = <0>;
1029 reg = <23>;
1030 };
1031 };
1032 };
1033
1034 rstc@fffffd00 {
1035 compatible = "atmel,at91sam9260-rstc";
1036 reg = <0xfffffd00 0x10>;
1037 clocks = <&clk32k>;
1038 };
1039
1040 shdwc@fffffd10 {
1041 compatible = "atmel,at91sam9260-shdwc";
1042 reg = <0xfffffd10 0x10>;
1043 clocks = <&clk32k>;
1044 };
1045
1046 pit: timer@fffffd30 {
1047 compatible = "atmel,at91sam9260-pit";
1048 reg = <0xfffffd30 0xf>;
1049 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
1050 clocks = <&mck>;
1051 };
1052
1053 watchdog@fffffd40 {
1054 compatible = "atmel,at91sam9260-wdt";
1055 reg = <0xfffffd40 0x10>;
1056 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
1057 clocks = <&clk32k>;
1058 status = "disabled";
1059 };
1060
1061 sckc@fffffd50 {
1062 compatible = "atmel,at91sam9x5-sckc";
1063 reg = <0xfffffd50 0x4>;
1064
1065 slow_osc: slow_osc {
1066 compatible = "atmel,at91sam9x5-clk-slow-osc";
1067 #clock-cells = <0>;
1068 atmel,startup-time-usec = <1200000>;
1069 clocks = <&slow_xtal>;
1070 };
1071
1072 slow_rc_osc: slow_rc_osc {
1073 compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
1074 #clock-cells = <0>;
1075 atmel,startup-time-usec = <75>;
1076 clock-frequency = <32768>;
1077 clock-accuracy = <50000000>;
1078 };
1079
1080 clk32k: slck {
1081 compatible = "atmel,at91sam9x5-clk-slow";
1082 #clock-cells = <0>;
1083 clocks = <&slow_rc_osc &slow_osc>;
1084 };
1085 };
1086
1087 rtc@fffffd20 {
1088 compatible = "atmel,at91sam9260-rtt";
1089 reg = <0xfffffd20 0x10>;
1090 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
1091 clocks = <&clk32k>;
1092 status = "disabled";
1093 };
1094
1095 gpbr: syscon@fffffd60 {
1096 compatible = "atmel,at91sam9260-gpbr", "syscon";
1097 reg = <0xfffffd60 0x10>;
1098 status = "disabled";
1099 };
1100
1101 rtc@fffffe00 {
1102 compatible = "atmel,at91rm9200-rtc";
1103 reg = <0xfffffe00 0x40>;
1104 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
1105 clocks = <&clk32k>;
1106 status = "disabled";
1107 };
1108
1109 };
1110 };
1111
1112 i2c-gpio-0 {
1113 compatible = "i2c-gpio";
1114 gpios = <&pioA 23 GPIO_ACTIVE_HIGH>, /* sda */
1115 <&pioA 24 GPIO_ACTIVE_HIGH>; /* scl */
1116 i2c-gpio,sda-open-drain;
1117 i2c-gpio,scl-open-drain;
1118 i2c-gpio,delay-us = <2>; /* ~100 kHz */
1119 #address-cells = <1>;
1120 #size-cells = <0>;
1121 pinctrl-names = "default";
1122 pinctrl-0 = <&pinctrl_i2c_gpio0>;
1123 status = "disabled";
1124 };
1125
1126 i2c-gpio-1 {
1127 compatible = "i2c-gpio";
1128 gpios = <&pioD 10 GPIO_ACTIVE_HIGH>, /* sda */
1129 <&pioD 11 GPIO_ACTIVE_HIGH>; /* scl */
1130 i2c-gpio,sda-open-drain;
1131 i2c-gpio,scl-open-drain;
1132 i2c-gpio,delay-us = <2>; /* ~100 kHz */
1133 #address-cells = <1>;
1134 #size-cells = <0>;
1135 pinctrl-names = "default";
1136 pinctrl-0 = <&pinctrl_i2c_gpio1>;
1137 status = "disabled";
1138 };
1139};