Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Wang Dongsheng | 9fdaa5c | 2014-03-19 10:47:55 +0800 | [diff] [blame] | 2 | /* |
| 3 | * Copyright 2014 Freescale Semiconductor, Inc. |
Biwen Li | d15aa9f | 2019-12-31 15:33:44 +0800 | [diff] [blame] | 4 | * Copyright 2019 NXP |
Wang Dongsheng | 9fdaa5c | 2014-03-19 10:47:55 +0800 | [diff] [blame] | 5 | * Authors: Priyanka Jain <Priyanka.Jain@freescale.com> |
| 6 | * Wang Dongsheng <dongsheng.wang@freescale.com> |
| 7 | * |
| 8 | * This file is copied and modified from the original t1040qds/diu.c. |
| 9 | * Encoder can be used in T104x and LSx Platform. |
Wang Dongsheng | 9fdaa5c | 2014-03-19 10:47:55 +0800 | [diff] [blame] | 10 | */ |
| 11 | |
| 12 | #include <common.h> |
| 13 | #include <stdio_dev.h> |
| 14 | #include <i2c.h> |
Simon Glass | dbd7954 | 2020-05-10 11:40:11 -0600 | [diff] [blame] | 15 | #include <linux/delay.h> |
Wang Dongsheng | 9fdaa5c | 2014-03-19 10:47:55 +0800 | [diff] [blame] | 16 | |
| 17 | #define I2C_DVI_INPUT_DATA_FORMAT_REG 0x1F |
| 18 | #define I2C_DVI_PLL_CHARGE_CNTL_REG 0x33 |
| 19 | #define I2C_DVI_PLL_DIVIDER_REG 0x34 |
| 20 | #define I2C_DVI_PLL_SUPPLY_CNTL_REG 0x35 |
| 21 | #define I2C_DVI_PLL_FILTER_REG 0x36 |
| 22 | #define I2C_DVI_TEST_PATTERN_REG 0x48 |
| 23 | #define I2C_DVI_POWER_MGMT_REG 0x49 |
| 24 | #define I2C_DVI_LOCK_STATE_REG 0x4D |
| 25 | #define I2C_DVI_SYNC_POLARITY_REG 0x56 |
| 26 | |
| 27 | /* |
| 28 | * Set VSYNC/HSYNC to active high. This is polarity of sync signals |
| 29 | * from DIU->DVI. The DIU default is active igh, so DVI is set to |
| 30 | * active high. |
| 31 | */ |
| 32 | #define I2C_DVI_INPUT_DATA_FORMAT_VAL 0x98 |
| 33 | |
| 34 | #define I2C_DVI_PLL_CHARGE_CNTL_HIGH_SPEED_VAL 0x06 |
| 35 | #define I2C_DVI_PLL_DIVIDER_HIGH_SPEED_VAL 0x26 |
| 36 | #define I2C_DVI_PLL_FILTER_HIGH_SPEED_VAL 0xA0 |
| 37 | #define I2C_DVI_PLL_CHARGE_CNTL_LOW_SPEED_VAL 0x08 |
| 38 | #define I2C_DVI_PLL_DIVIDER_LOW_SPEED_VAL 0x16 |
| 39 | #define I2C_DVI_PLL_FILTER_LOW_SPEED_VAL 0x60 |
| 40 | |
| 41 | /* Clear test pattern */ |
| 42 | #define I2C_DVI_TEST_PATTERN_VAL 0x18 |
| 43 | /* Exit Power-down mode */ |
| 44 | #define I2C_DVI_POWER_MGMT_VAL 0xC0 |
| 45 | |
| 46 | /* Monitor polarity is handled via DVI Sync Polarity Register */ |
| 47 | #define I2C_DVI_SYNC_POLARITY_VAL 0x00 |
| 48 | |
| 49 | /* Programming of HDMI Chrontel CH7301 connector */ |
| 50 | int diu_set_dvi_encoder(unsigned int pixclock) |
| 51 | { |
| 52 | int ret; |
| 53 | u8 temp; |
| 54 | |
| 55 | temp = I2C_DVI_TEST_PATTERN_VAL; |
Igor Opaniuk | f7c9176 | 2021-02-09 13:52:45 +0200 | [diff] [blame] | 56 | #if CONFIG_IS_ENABLED(DM_I2C) |
Biwen Li | d15aa9f | 2019-12-31 15:33:44 +0800 | [diff] [blame] | 57 | struct udevice *dev; |
| 58 | |
| 59 | ret = i2c_get_chip_for_busnum(CONFIG_SYS_I2C_DVI_BUS_NUM, |
| 60 | CONFIG_SYS_I2C_DVI_ADDR, |
| 61 | 1, &dev); |
| 62 | if (ret) { |
| 63 | printf("%s: Cannot find udev for a bus %d\n", __func__, |
| 64 | CONFIG_SYS_I2C_DVI_BUS_NUM); |
| 65 | return ret; |
| 66 | } |
| 67 | ret = dm_i2c_write(dev, I2C_DVI_TEST_PATTERN_REG, &temp, 1); |
| 68 | if (ret) { |
| 69 | puts("I2C: failed to select proper dvi test pattern\n"); |
| 70 | return ret; |
| 71 | } |
| 72 | temp = I2C_DVI_INPUT_DATA_FORMAT_VAL; |
| 73 | ret = dm_i2c_write(dev, I2C_DVI_INPUT_DATA_FORMAT_REG, &temp, 1); |
| 74 | if (ret) { |
| 75 | puts("I2C: failed to select dvi input data format\n"); |
| 76 | return ret; |
| 77 | } |
| 78 | |
| 79 | /* Set Sync polarity register */ |
| 80 | temp = I2C_DVI_SYNC_POLARITY_VAL; |
| 81 | ret = dm_i2c_write(dev, I2C_DVI_SYNC_POLARITY_REG, &temp, 1); |
| 82 | if (ret) { |
| 83 | puts("I2C: failed to select dvi syc polarity\n"); |
| 84 | return ret; |
| 85 | } |
| 86 | |
| 87 | /* Set PLL registers based on pixel clock rate*/ |
| 88 | if (pixclock > 65000000) { |
| 89 | temp = I2C_DVI_PLL_CHARGE_CNTL_HIGH_SPEED_VAL; |
| 90 | ret = dm_i2c_write(dev, I2C_DVI_PLL_CHARGE_CNTL_REG, &temp, 1); |
| 91 | if (ret) { |
| 92 | puts("I2C: failed to select dvi pll charge_cntl\n"); |
| 93 | return ret; |
| 94 | } |
| 95 | temp = I2C_DVI_PLL_DIVIDER_HIGH_SPEED_VAL; |
| 96 | ret = dm_i2c_write(dev, I2C_DVI_PLL_DIVIDER_REG, &temp, 1); |
| 97 | if (ret) { |
| 98 | puts("I2C: failed to select dvi pll divider\n"); |
| 99 | return ret; |
| 100 | } |
| 101 | temp = I2C_DVI_PLL_FILTER_HIGH_SPEED_VAL; |
| 102 | ret = dm_i2c_write(dev, I2C_DVI_PLL_FILTER_REG, &temp, 1); |
| 103 | if (ret) { |
| 104 | puts("I2C: failed to select dvi pll filter\n"); |
| 105 | return ret; |
| 106 | } |
| 107 | } else { |
| 108 | temp = I2C_DVI_PLL_CHARGE_CNTL_LOW_SPEED_VAL; |
| 109 | ret = dm_i2c_write(dev, I2C_DVI_PLL_CHARGE_CNTL_REG, &temp, 1); |
| 110 | if (ret) { |
| 111 | puts("I2C: failed to select dvi pll charge_cntl\n"); |
| 112 | return ret; |
| 113 | } |
| 114 | temp = I2C_DVI_PLL_DIVIDER_LOW_SPEED_VAL; |
| 115 | ret = dm_i2c_write(dev, I2C_DVI_PLL_DIVIDER_REG, &temp, 1); |
| 116 | if (ret) { |
| 117 | puts("I2C: failed to select dvi pll divider\n"); |
| 118 | return ret; |
| 119 | } |
| 120 | temp = I2C_DVI_PLL_FILTER_LOW_SPEED_VAL; |
| 121 | ret = dm_i2c_write(dev, I2C_DVI_PLL_FILTER_REG, &temp, 1); |
| 122 | if (ret) { |
| 123 | puts("I2C: failed to select dvi pll filter\n"); |
| 124 | return ret; |
| 125 | } |
| 126 | } |
| 127 | |
| 128 | temp = I2C_DVI_POWER_MGMT_VAL; |
| 129 | ret = dm_i2c_write(dev, I2C_DVI_POWER_MGMT_REG, &temp, 1); |
| 130 | if (ret) { |
| 131 | puts("I2C: failed to select dvi power mgmt\n"); |
| 132 | return ret; |
| 133 | } |
| 134 | #else |
Wang Dongsheng | 9fdaa5c | 2014-03-19 10:47:55 +0800 | [diff] [blame] | 135 | ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_TEST_PATTERN_REG, 1, |
| 136 | &temp, 1); |
| 137 | if (ret) { |
| 138 | puts("I2C: failed to select proper dvi test pattern\n"); |
| 139 | return ret; |
| 140 | } |
| 141 | temp = I2C_DVI_INPUT_DATA_FORMAT_VAL; |
| 142 | ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_INPUT_DATA_FORMAT_REG, |
| 143 | 1, &temp, 1); |
| 144 | if (ret) { |
| 145 | puts("I2C: failed to select dvi input data format\n"); |
| 146 | return ret; |
| 147 | } |
| 148 | |
| 149 | /* Set Sync polarity register */ |
| 150 | temp = I2C_DVI_SYNC_POLARITY_VAL; |
| 151 | ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_SYNC_POLARITY_REG, 1, |
| 152 | &temp, 1); |
| 153 | if (ret) { |
| 154 | puts("I2C: failed to select dvi syc polarity\n"); |
| 155 | return ret; |
| 156 | } |
| 157 | |
| 158 | /* Set PLL registers based on pixel clock rate*/ |
| 159 | if (pixclock > 65000000) { |
| 160 | temp = I2C_DVI_PLL_CHARGE_CNTL_HIGH_SPEED_VAL; |
| 161 | ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, |
| 162 | I2C_DVI_PLL_CHARGE_CNTL_REG, 1, &temp, 1); |
| 163 | if (ret) { |
| 164 | puts("I2C: failed to select dvi pll charge_cntl\n"); |
| 165 | return ret; |
| 166 | } |
| 167 | temp = I2C_DVI_PLL_DIVIDER_HIGH_SPEED_VAL; |
| 168 | ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, |
| 169 | I2C_DVI_PLL_DIVIDER_REG, 1, &temp, 1); |
| 170 | if (ret) { |
| 171 | puts("I2C: failed to select dvi pll divider\n"); |
| 172 | return ret; |
| 173 | } |
| 174 | temp = I2C_DVI_PLL_FILTER_HIGH_SPEED_VAL; |
| 175 | ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, |
| 176 | I2C_DVI_PLL_FILTER_REG, 1, &temp, 1); |
| 177 | if (ret) { |
| 178 | puts("I2C: failed to select dvi pll filter\n"); |
| 179 | return ret; |
| 180 | } |
| 181 | } else { |
| 182 | temp = I2C_DVI_PLL_CHARGE_CNTL_LOW_SPEED_VAL; |
| 183 | ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, |
| 184 | I2C_DVI_PLL_CHARGE_CNTL_REG, 1, &temp, 1); |
| 185 | if (ret) { |
| 186 | puts("I2C: failed to select dvi pll charge_cntl\n"); |
| 187 | return ret; |
| 188 | } |
| 189 | temp = I2C_DVI_PLL_DIVIDER_LOW_SPEED_VAL; |
| 190 | ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, |
| 191 | I2C_DVI_PLL_DIVIDER_REG, 1, &temp, 1); |
| 192 | if (ret) { |
| 193 | puts("I2C: failed to select dvi pll divider\n"); |
| 194 | return ret; |
| 195 | } |
| 196 | temp = I2C_DVI_PLL_FILTER_LOW_SPEED_VAL; |
| 197 | ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, |
| 198 | I2C_DVI_PLL_FILTER_REG, 1, &temp, 1); |
| 199 | if (ret) { |
| 200 | puts("I2C: failed to select dvi pll filter\n"); |
| 201 | return ret; |
| 202 | } |
| 203 | } |
| 204 | |
| 205 | temp = I2C_DVI_POWER_MGMT_VAL; |
| 206 | ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_POWER_MGMT_REG, 1, |
| 207 | &temp, 1); |
| 208 | if (ret) { |
| 209 | puts("I2C: failed to select dvi power mgmt\n"); |
| 210 | return ret; |
| 211 | } |
Biwen Li | d15aa9f | 2019-12-31 15:33:44 +0800 | [diff] [blame] | 212 | #endif |
Wang Dongsheng | 9fdaa5c | 2014-03-19 10:47:55 +0800 | [diff] [blame] | 213 | |
| 214 | udelay(500); |
| 215 | |
| 216 | return 0; |
| 217 | } |