| Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| Stefan Roese | bf5ed2e | 2015-11-18 11:06:09 +0100 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2015 Stefan Roese <sr@denx.de> |
| Stefan Roese | bf5ed2e | 2015-11-18 11:06:09 +0100 | [diff] [blame] | 4 | */ |
| 5 | #ifndef __CONFIG_SOCFPGA_SR1500_H__ |
| 6 | #define __CONFIG_SOCFPGA_SR1500_H__ |
| 7 | |
| 8 | #include <asm/arch/base_addr_ac5.h> |
| 9 | |
| Stefan Roese | bf5ed2e | 2015-11-18 11:06:09 +0100 | [diff] [blame] | 10 | /* Memory configurations */ |
| 11 | #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SR1500 */ |
| 12 | |
| Stefan Roese | bf5ed2e | 2015-11-18 11:06:09 +0100 | [diff] [blame] | 13 | /* Ethernet on SoC (EMAC) */ |
| 14 | #define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII |
| 15 | /* The PHY is autodetected, so no MII PHY address is needed here */ |
| Stefan Roese | bf5ed2e | 2015-11-18 11:06:09 +0100 | [diff] [blame] | 16 | #define PHY_ANEG_TIMEOUT 8000 |
| 17 | |
| Stefan Roese | bf5ed2e | 2015-11-18 11:06:09 +0100 | [diff] [blame] | 18 | /* Enable SPI NOR flash reset, needed for SPI booting */ |
| 19 | #define CONFIG_SPI_N25Q256A_RESET |
| 20 | |
| 21 | /* |
| 22 | * Bootcounter |
| 23 | */ |
| Stefan Roese | bf5ed2e | 2015-11-18 11:06:09 +0100 | [diff] [blame] | 24 | #define CONFIG_SYS_BOOTCOUNT_BE |
| 25 | |
| Stefan Roese | bf5ed2e | 2015-11-18 11:06:09 +0100 | [diff] [blame] | 26 | /* Environment setting for SPI flash */ |
| Stefan Roese | 85e8439 | 2016-03-03 16:57:39 +0100 | [diff] [blame] | 27 | |
| Marek Vasut | 4003fe2 | 2016-02-26 19:11:30 +0100 | [diff] [blame] | 28 | /* The rest of the configuration is shared */ |
| 29 | #include <configs/socfpga_common.h> |
| 30 | |
| Stefan Roese | bf5ed2e | 2015-11-18 11:06:09 +0100 | [diff] [blame] | 31 | #endif /* __CONFIG_SOCFPGA_SR1500_H__ */ |