| Gilles Talis | 29a8e33 | 2024-10-27 10:52:41 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | /* |
| 3 | * Copyright 2019 NXP |
| 4 | * Copyright 2024 Gilles Talis <gilles.talis@gmail.com> |
| 5 | */ |
| 6 | |
| 7 | #ifndef __IMX8MP_NAVQP_H |
| 8 | #define __IMX8MP_NAVQP_H |
| 9 | |
| 10 | #include <linux/sizes.h> |
| 11 | #include <asm/arch/imx-regs.h> |
| 12 | |
| 13 | #define CFG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) |
| 14 | |
| 15 | #define BOOT_TARGET_DEVICES(func) \ |
| 16 | func(MMC, mmc, 1) \ |
| 17 | func(MMC, mmc, 2) |
| 18 | |
| 19 | #include <config_distro_bootcmd.h> |
| 20 | |
| 21 | /* Initial environment variables */ |
| 22 | #define CFG_EXTRA_ENV_SETTINGS \ |
| 23 | BOOTENV |
| 24 | |
| 25 | /* Link Definitions */ |
| 26 | |
| 27 | #define CFG_SYS_INIT_RAM_ADDR 0x40000000 |
| 28 | #define CFG_SYS_INIT_RAM_SIZE 0x80000 |
| 29 | |
| 30 | /* 8GB DDR */ |
| 31 | #define CFG_SYS_SDRAM_BASE 0x40000000 |
| 32 | #define PHYS_SDRAM 0x40000000 |
| 33 | #define PHYS_SDRAM_SIZE 0xC0000000 /* 3 GB */ |
| 34 | #define PHYS_SDRAM_2 0x100000000 |
| 35 | #define PHYS_SDRAM_2_SIZE 0x140000000 /* 5 GB */ |
| 36 | |
| 37 | #endif |