blob: 4454061e071b65b6d9156d69019b3e56441679dc [file] [log] [blame]
Marek Vasutb700f032019-07-29 19:59:44 +02001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * board/renesas/condor/condor.c
4 * This file is Condor board support.
5 *
6 * Copyright (C) 2019 Marek Vasut <marek.vasut+renesas@gmail.com>
7 */
8
9#include <common.h>
Simon Glassafb02152019-12-28 10:45:01 -070010#include <cpu_func.h>
Simon Glassf11478f2019-12-28 10:45:07 -070011#include <hang.h>
Simon Glass97589732020-05-10 11:40:02 -060012#include <init.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060013#include <asm/global_data.h>
Marek Vasutb700f032019-07-29 19:59:44 +020014#include <asm/processor.h>
15#include <asm/mach-types.h>
16#include <asm/io.h>
17#include <linux/errno.h>
18#include <asm/arch/sys_proto.h>
19
20DECLARE_GLOBAL_DATA_PTR;
21
Marek Vasutb700f032019-07-29 19:59:44 +020022int board_init(void)
23{
24 /* adress of boot parameters */
25 gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000;
26
27 return 0;
28}
29
30#define RST_BASE 0xE6160000
31#define RST_CA57RESCNT (RST_BASE + 0x40)
32#define RST_CA53RESCNT (RST_BASE + 0x44)
33#define RST_RSTOUTCR (RST_BASE + 0x58)
34#define RST_CA57_CODE 0xA5A5000F
35#define RST_CA53_CODE 0x5A5A000F
36
37void reset_cpu(ulong addr)
38{
39 unsigned long midr, cputype;
40
41 asm volatile("mrs %0, midr_el1" : "=r" (midr));
42 cputype = (midr >> 4) & 0xfff;
43
44 if (cputype == 0xd03)
45 writel(RST_CA53_CODE, RST_CA53RESCNT);
46 else if (cputype == 0xd07)
47 writel(RST_CA57_CODE, RST_CA57RESCNT);
48 else
49 hang();
50}