Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Marek Vasut | b09c8bf | 2013-09-20 16:14:13 +0200 | [diff] [blame] | 2 | /* |
| 3 | * PPC-AG BG0900 board |
| 4 | * |
| 5 | * Copyright (C) 2013 Marek Vasut <marex@denx.de> |
Marek Vasut | b09c8bf | 2013-09-20 16:14:13 +0200 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #include <common.h> |
Simon Glass | 9758973 | 2020-05-10 11:40:02 -0600 | [diff] [blame] | 9 | #include <init.h> |
Simon Glass | 274e0b0 | 2020-05-10 11:39:56 -0600 | [diff] [blame] | 10 | #include <net.h> |
Simon Glass | 3ba929a | 2020-10-30 21:38:53 -0600 | [diff] [blame^] | 11 | #include <asm/global_data.h> |
Marek Vasut | b09c8bf | 2013-09-20 16:14:13 +0200 | [diff] [blame] | 12 | #include <asm/gpio.h> |
| 13 | #include <asm/io.h> |
| 14 | #include <asm/arch/imx-regs.h> |
| 15 | #include <asm/arch/iomux-mx28.h> |
| 16 | #include <asm/arch/clock.h> |
| 17 | #include <asm/arch/sys_proto.h> |
Simon Glass | dbd7954 | 2020-05-10 11:40:11 -0600 | [diff] [blame] | 18 | #include <linux/delay.h> |
Marek Vasut | b09c8bf | 2013-09-20 16:14:13 +0200 | [diff] [blame] | 19 | #include <linux/mii.h> |
| 20 | #include <miiphy.h> |
| 21 | #include <netdev.h> |
| 22 | #include <errno.h> |
| 23 | |
| 24 | DECLARE_GLOBAL_DATA_PTR; |
| 25 | |
| 26 | /* |
| 27 | * Functions |
| 28 | */ |
| 29 | int board_early_init_f(void) |
| 30 | { |
| 31 | /* IO0 clock at 480MHz */ |
| 32 | mxs_set_ioclk(MXC_IOCLK0, 480000); |
| 33 | /* IO1 clock at 480MHz */ |
| 34 | mxs_set_ioclk(MXC_IOCLK1, 480000); |
| 35 | |
| 36 | /* SSP2 clock at 160MHz */ |
| 37 | mxs_set_sspclk(MXC_SSPCLK2, 160000, 0); |
| 38 | |
| 39 | return 0; |
| 40 | } |
| 41 | |
| 42 | int dram_init(void) |
| 43 | { |
| 44 | return mxs_dram_init(); |
| 45 | } |
| 46 | |
| 47 | int board_init(void) |
| 48 | { |
| 49 | /* Adress of boot parameters */ |
| 50 | gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; |
| 51 | |
| 52 | return 0; |
| 53 | } |
| 54 | |
| 55 | #ifdef CONFIG_CMD_NET |
Masahiro Yamada | f7ed78b | 2020-06-26 15:13:33 +0900 | [diff] [blame] | 56 | int board_eth_init(struct bd_info *bis) |
Marek Vasut | b09c8bf | 2013-09-20 16:14:13 +0200 | [diff] [blame] | 57 | { |
| 58 | struct mxs_clkctrl_regs *clkctrl_regs = |
| 59 | (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; |
| 60 | struct eth_device *dev; |
| 61 | int ret; |
| 62 | |
| 63 | ret = cpu_eth_init(bis); |
| 64 | |
| 65 | /* BG0900 uses ENET_CLK PAD to drive FEC clock */ |
| 66 | writel(CLKCTRL_ENET_TIME_SEL_RMII_CLK | CLKCTRL_ENET_CLK_OUT_EN, |
| 67 | &clkctrl_regs->hw_clkctrl_enet); |
| 68 | |
| 69 | /* Reset FEC PHYs */ |
| 70 | gpio_direction_output(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 0); |
| 71 | udelay(200); |
| 72 | gpio_set_value(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 1); |
| 73 | |
| 74 | ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE); |
| 75 | if (ret) { |
| 76 | puts("FEC MXS: Unable to init FEC0\n"); |
| 77 | return ret; |
| 78 | } |
| 79 | |
| 80 | dev = eth_get_dev_by_name("FEC0"); |
| 81 | if (!dev) { |
| 82 | puts("FEC MXS: Unable to get FEC0 device entry\n"); |
| 83 | return -EINVAL; |
| 84 | } |
| 85 | |
| 86 | return ret; |
| 87 | } |
| 88 | |
| 89 | #endif |