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git01.mediatek.com / filogic / uboot / 3ba929a7e570f64fa6873144e9b12ffa6b02f052 / . / arch / mips / mach-ath79 / qca953x / clk.c
blob: f5438ef1c8d9b6493cebefbdd9df55d24d19e482 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Wills Wang6b83b442016-03-16 16:59:54 +0800[diff] [blame]2/*
3 * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
Wills Wang6b83b442016-03-16 16:59:54 +0800[diff] [blame]4 */
5
6#include <common.h>
Simon Glass85d65312019-12-28 10:44:58 -0700[diff] [blame]7#include <clock_legacy.h>
Simon Glass3ba929a2020-10-30 21:38:53 -0600[diff] [blame^]8#include <asm/global_data.h>
Wills Wang6b83b442016-03-16 16:59:54 +0800[diff] [blame]9#include <asm/io.h>
10#include <asm/addrspace.h>
11#include <asm/types.h>
12#include <mach/ar71xx_regs.h>
Wills Wangddc05522016-05-30 22:54:50 +0800[diff] [blame]13#include <mach/ath79.h>
Wills Wang6b83b442016-03-16 16:59:54 +0800[diff] [blame]14
15DECLARE_GLOBAL_DATA_PTR;
16
17static u32 qca953x_get_xtal(void)
18{
19 u32 val;
20
Wills Wangddc05522016-05-30 22:54:50 +0800[diff] [blame]21 val = ath79_get_bootstrap();
Wills Wang6b83b442016-03-16 16:59:54 +0800[diff] [blame]22 if (val & QCA953X_BOOTSTRAP_REF_CLK_40)
23 return 40000000;
24 else
25 return 25000000;
26}
27
28int get_serial_clock(void)
29{
30 return qca953x_get_xtal();
31}
32
33int get_clocks(void)
34{
35 void __iomem *regs;
36 u32 val, ctrl, xtal, pll, div;
37
38 regs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
39 MAP_NOCACHE);
40
41 xtal = qca953x_get_xtal();
42 ctrl = readl(regs + QCA953X_PLL_CLK_CTRL_REG);
43 val = readl(regs + QCA953X_PLL_CPU_CONFIG_REG);
44
45 /* VCOOUT = XTAL * DIV_INT */
46 div = (val >> QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT)
47 & QCA953X_PLL_CPU_CONFIG_REFDIV_MASK;
48 pll = xtal / div;
49
50 /* PLLOUT = VCOOUT * (1/2^OUTDIV) */
51 div = (val >> QCA953X_PLL_CPU_CONFIG_NINT_SHIFT)
52 & QCA953X_PLL_CPU_CONFIG_NINT_MASK;
53 pll *= div;
54 div = (val >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT)
55 & QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK;
56 if (!div)
57 div = 1;
58 pll >>= div;
59
60 /* CPU_CLK = PLLOUT / CPU_POST_DIV */
61 div = ((ctrl >> QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT)
62 & QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK) + 1;
63 gd->cpu_clk = pll / div;
64
65
66 val = readl(regs + QCA953X_PLL_DDR_CONFIG_REG);
67 /* VCOOUT = XTAL * DIV_INT */
68 div = (val >> QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT)
69 & QCA953X_PLL_DDR_CONFIG_REFDIV_MASK;
70 pll = xtal / div;
71
72 /* PLLOUT = VCOOUT * (1/2^OUTDIV) */
73 div = (val >> QCA953X_PLL_DDR_CONFIG_NINT_SHIFT)
74 & QCA953X_PLL_DDR_CONFIG_NINT_MASK;
75 pll *= div;
76 div = (val >> QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT)
77 & QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK;
78 if (!div)
79 div = 1;
80 pll >>= div;
81
82 /* DDR_CLK = PLLOUT / DDR_POST_DIV */
83 div = ((ctrl >> QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT)
84 & QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK) + 1;
85 gd->mem_clk = pll / div;
86
87 div = ((ctrl >> QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT)
88 & QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK) + 1;
89 if (ctrl & QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL) {
90 /* AHB_CLK = DDR_CLK / AHB_POST_DIV */
91 gd->bus_clk = gd->mem_clk / (div + 1);
92 } else {
93 /* AHB_CLK = CPU_CLK / AHB_POST_DIV */
94 gd->bus_clk = gd->cpu_clk / (div + 1);
95 }
96
97 return 0;
98}
99
100ulong get_bus_freq(ulong dummy)
101{
102 if (!gd->bus_clk)
103 get_clocks();
104 return gd->bus_clk;
105}
106
107ulong get_ddr_freq(ulong dummy)
108{
109 if (!gd->mem_clk)
110 get_clocks();
111 return gd->mem_clk;
112}