blob: bab375e18acc9b32e185dfd127f333f1a5b1f2b6 [file] [log] [blame]
Marek BehĂșne577cc32020-04-08 19:25:18 +02001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2016 Stefan Roese <sr@denx.de>
4 */
5
6#include <common.h>
7#include <asm/arch/cpu.h>
8#include <asm/arch/soc.h>
Simon Glass3ba929a2020-10-30 21:38:53 -06009#include <asm/global_data.h>
Simon Glass6b9f0102020-05-10 11:40:06 -060010#include <asm/ptrace.h>
Marek BehĂșne577cc32020-04-08 19:25:18 +020011#include <asm/system.h>
12#include <linux/sizes.h>
13
14DECLARE_GLOBAL_DATA_PTR;
15
16#define MV_SIP_DRAM_SIZE 0x82000010
17
18u64 a8k_dram_scan_ap_sz(void)
19{
20 struct pt_regs pregs;
21
22 pregs.regs[0] = MV_SIP_DRAM_SIZE;
23 pregs.regs[1] = SOC_REGS_PHY_BASE;
24 smc_call(&pregs);
25
26 return pregs.regs[0];
27}
28
29int a8k_dram_init_banksize(void)
30{
31 /*
32 * The firmware (ATF) leaves a 1G whole above the 3G mark for IO
33 * devices. Higher RAM is mapped at 4G.
34 *
35 * Config 2 DRAM banks:
36 * Bank 0 - max size 4G - 1G
37 * Bank 1 - ram size - 4G + 1G
38 */
39 phys_size_t max_bank0_size = SZ_4G - SZ_1G;
40
41 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
42 if (gd->ram_size <= max_bank0_size) {
43 gd->bd->bi_dram[0].size = gd->ram_size;
44 return 0;
45 }
46
47 gd->bd->bi_dram[0].size = max_bank0_size;
48 if (CONFIG_NR_DRAM_BANKS > 1) {
49 gd->bd->bi_dram[1].start = SZ_4G;
50 gd->bd->bi_dram[1].size = gd->ram_size - max_bank0_size;
51 }
52
53 return 0;
54}