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gaurav ranaf79323c2015-03-10 14:08:50 +05301/*
2 * Copyright 2015 Freescale Semiconductor, Inc.
Sumit Garg666bbd02017-08-16 07:13:28 -04003 * Copyright 2017 NXP
gaurav ranaf79323c2015-03-10 14:08:50 +05304 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#ifndef __FSL_SECURE_BOOT_H
9#define __FSL_SECURE_BOOT_H
10
Aneesh Bansal43104702016-01-22 16:37:24 +053011#ifdef CONFIG_CHAIN_OF_TRUST
Aneesh Bansald31bb3e2015-07-31 14:10:03 +053012#define CONFIG_FSL_SEC_MON
Aneesh Bansald31bb3e2015-07-31 14:10:03 +053013
Simon Glass3aa66122016-09-12 23:18:23 -060014#ifdef CONFIG_SPL_BUILD
Sumit Gargbdddd6e2016-06-14 13:52:38 -040015/*
16 * Define the key hash for U-Boot here if public/private key pair used to
17 * sign U-boot are different from the SRK hash put in the fuse
18 * Example of defining KEY_HASH is
19 * #define CONFIG_SPL_UBOOT_KEY_HASH \
20 * "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b"
21 * else leave it defined as NULL
22 */
23
24#define CONFIG_SPL_UBOOT_KEY_HASH NULL
25#endif /* ifdef CONFIG_SPL_BUILD */
26
Ruchika Guptad6b89202017-04-17 18:07:17 +053027#define CONFIG_KEY_REVOCATION
28
Sumit Gargbdddd6e2016-06-14 13:52:38 -040029#ifndef CONFIG_SPL_BUILD
Aneesh Bansald31bb3e2015-07-31 14:10:03 +053030#ifndef CONFIG_SYS_RAMBOOT
31/* The key used for verification of next level images
32 * is picked up from an Extension Table which has
33 * been verified by the ISBC (Internal Secure boot Code)
34 * in boot ROM of the SoC.
35 * The feature is only applicable in case of NOR boot and is
36 * not applicable in case of RAMBOOT (NAND, SD, SPI).
Udit Agarwal990a9972017-02-09 21:36:11 +053037 * For LS, this feature is available for all device if IE Table
38 * is copied to XIP memory
39 * Also, for LS, ISBC doesn't verify this table.
Aneesh Bansald31bb3e2015-07-31 14:10:03 +053040 */
41#define CONFIG_FSL_ISBC_KEY_EXT
Aneesh Bansald31bb3e2015-07-31 14:10:03 +053042
Saksham Jain6121f082016-03-23 16:24:34 +053043#endif
44
Vinitha Pillai-B572238a3c6452017-03-23 13:48:16 +053045#if defined(CONFIG_FSL_LAYERSCAPE)
46/*
47 * For fsl layerscape based platforms, ESBC image Address in Header
48 * is 64 bit.
Saksham Jainc0c38d22016-03-23 16:24:35 +053049 */
Aneesh Bansal962021a2016-01-22 16:37:22 +053050#define CONFIG_ESBC_ADDR_64BIT
51#endif
52
York Sun4ce6fbf2017-03-27 11:41:01 -070053#ifdef CONFIG_ARCH_LS2080A
Saksham Jainf0eb2ca2016-03-23 16:24:38 +053054#define CONFIG_EXTRA_ENV \
55 "setenv fdt_high 0xa0000000;" \
56 "setenv initrd_high 0xcfffffff;" \
57 "setenv hwconfig \'fsl_ddr:ctlr_intlv=null,bank_intlv=null\';"
58#else
gaurav ranaf79323c2015-03-10 14:08:50 +053059#define CONFIG_EXTRA_ENV \
Sumit Garg45642832016-06-14 13:52:39 -040060 "setenv fdt_high 0xffffffff;" \
61 "setenv initrd_high 0xffffffff;" \
gaurav ranaf79323c2015-03-10 14:08:50 +053062 "setenv hwconfig \'fsl_ddr:ctlr_intlv=null,bank_intlv=null\';"
Saksham Jainf0eb2ca2016-03-23 16:24:38 +053063#endif
gaurav ranaf79323c2015-03-10 14:08:50 +053064
Saksham Jain503eab92016-03-23 16:24:37 +053065/* Copying Bootscript and Header to DDR from NOR for LS2 and for rest, from
66 * Non-XIP Memory (Nand/SD)*/
Udit Agarwal6b29d232017-01-06 15:58:56 +053067#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_FSL_LSCH3) || \
Ruchika Guptaba688752017-04-17 18:07:18 +053068 defined(CONFIG_SD_BOOT) || defined(CONFIG_NAND_BOOT)
Saksham Jain503eab92016-03-23 16:24:37 +053069#define CONFIG_BOOTSCRIPT_COPY_RAM
70#endif
Sumit Garg45642832016-06-14 13:52:39 -040071/* The address needs to be modified according to NOR, NAND, SD and
72 * DDR memory map
73 */
Udit Agarwal6b29d232017-01-06 15:58:56 +053074#ifdef CONFIG_FSL_LSCH3
Udit Agarwalc83ea8a2017-08-16 07:13:29 -040075#ifdef CONFIG_QSPI_BOOT
76#define CONFIG_BS_ADDR_DEVICE 0x20600000
77#define CONFIG_BS_HDR_ADDR_DEVICE 0x20640000
78#else /* NOR BOOT */
Sumit Garg666bbd02017-08-16 07:13:28 -040079#define CONFIG_BS_ADDR_DEVICE 0x580600000
80#define CONFIG_BS_HDR_ADDR_DEVICE 0x580640000
Udit Agarwalc83ea8a2017-08-16 07:13:29 -040081#endif /*ifdef CONFIG_QSPI_BOOT */
Sumit Garg45642832016-06-14 13:52:39 -040082#define CONFIG_BS_SIZE 0x00001000
Sumit Garg666bbd02017-08-16 07:13:28 -040083#define CONFIG_BS_HDR_SIZE 0x00004000
84#define CONFIG_BS_ADDR_RAM 0xa0600000
85#define CONFIG_BS_HDR_ADDR_RAM 0xa0640000
Saksham Jain503eab92016-03-23 16:24:37 +053086#else
Sumit Garg45642832016-06-14 13:52:39 -040087#ifdef CONFIG_SD_BOOT
88/* For SD boot address and size are assigned in terms of sector
89 * offset and no. of sectors respectively.
90 */
Sumit Garg666bbd02017-08-16 07:13:28 -040091#define CONFIG_BS_ADDR_DEVICE 0x00003000
92#define CONFIG_BS_HDR_ADDR_DEVICE 0x00003200
Sumit Garg45642832016-06-14 13:52:39 -040093#define CONFIG_BS_SIZE 0x00000008
Sumit Garg666bbd02017-08-16 07:13:28 -040094#define CONFIG_BS_HDR_SIZE 0x00000010
Ruchika Guptaba688752017-04-17 18:07:18 +053095#elif defined(CONFIG_NAND_BOOT)
Sumit Garg666bbd02017-08-16 07:13:28 -040096#define CONFIG_BS_ADDR_DEVICE 0x00600000
97#define CONFIG_BS_HDR_ADDR_DEVICE 0x00640000
98#define CONFIG_BS_SIZE 0x00001000
Vinitha Pillai-B572238a3c6452017-03-23 13:48:16 +053099#define CONFIG_BS_HDR_SIZE 0x00002000
Sumit Garg666bbd02017-08-16 07:13:28 -0400100#elif defined(CONFIG_QSPI_BOOT)
101#define CONFIG_BS_ADDR_DEVICE 0x40600000
102#define CONFIG_BS_HDR_ADDR_DEVICE 0x40640000
Vinitha Pillai-B572238a3c6452017-03-23 13:48:16 +0530103#define CONFIG_BS_SIZE 0x00001000
Sumit Garg45642832016-06-14 13:52:39 -0400104#define CONFIG_BS_HDR_SIZE 0x00002000
Sumit Garg666bbd02017-08-16 07:13:28 -0400105#else /* Default NOR Boot */
106#define CONFIG_BS_ADDR_DEVICE 0x60600000
107#define CONFIG_BS_HDR_ADDR_DEVICE 0x60640000
Sumit Garg45642832016-06-14 13:52:39 -0400108#define CONFIG_BS_SIZE 0x00001000
Sumit Garg666bbd02017-08-16 07:13:28 -0400109#define CONFIG_BS_HDR_SIZE 0x00002000
Vinitha Pillai-B572238a3c6452017-03-23 13:48:16 +0530110#endif
Sumit Garg666bbd02017-08-16 07:13:28 -0400111#define CONFIG_BS_ADDR_RAM 0x81000000
112#define CONFIG_BS_HDR_ADDR_RAM 0x81020000
Saksham Jain503eab92016-03-23 16:24:37 +0530113#endif
114
115#ifdef CONFIG_BOOTSCRIPT_COPY_RAM
Saksham Jain503eab92016-03-23 16:24:37 +0530116#define CONFIG_BOOTSCRIPT_ADDR CONFIG_BS_ADDR_RAM
Sumit Garg666bbd02017-08-16 07:13:28 -0400117#define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_RAM
Saksham Jain506c2eb2016-03-23 16:24:36 +0530118#else
Sumit Garg45642832016-06-14 13:52:39 -0400119#define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_DEVICE
120/* BOOTSCRIPT_ADDR is not required */
Saksham Jain506c2eb2016-03-23 16:24:36 +0530121#endif
gaurav ranaf79323c2015-03-10 14:08:50 +0530122
Sumit Garge0f9e9b2016-09-01 12:56:44 -0400123#ifdef CONFIG_FSL_LS_PPA
Sumit Garge0f9e9b2016-09-01 12:56:44 -0400124/* Define the key hash here if SRK used for signing PPA image is
125 * different from SRK hash put in SFP used for U-Boot.
126 * Example
Vinitha Pillai-B57223a4b3ded2017-03-23 13:48:14 +0530127 * #define PPA_KEY_HASH \
Sumit Garge0f9e9b2016-09-01 12:56:44 -0400128 * "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b"
129 */
Vinitha Pillai-B57223a4b3ded2017-03-23 13:48:14 +0530130#define PPA_KEY_HASH NULL
Sumit Garge0f9e9b2016-09-01 12:56:44 -0400131#endif /* ifdef CONFIG_FSL_LS_PPA */
132
Aneesh Bansal43104702016-01-22 16:37:24 +0530133#include <config_fsl_chain_trust.h>
Sumit Gargbdddd6e2016-06-14 13:52:38 -0400134#endif /* #ifndef CONFIG_SPL_BUILD */
Aneesh Bansal43104702016-01-22 16:37:24 +0530135#endif /* #ifdef CONFIG_CHAIN_OF_TRUST */
gaurav ranaf79323c2015-03-10 14:08:50 +0530136#endif