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git01.mediatek.com / filogic / uboot / 3ba69480cf07fd3970d7cd4e5449cd42add16081 / . / arch / arm / include / asm / arch-rockchip / sdram_rk3399.h
blob: 22a6ca9ae1cd6ac8482cdb1dece5c30650dcc558 [file] [log] [blame]
Kever Yang50fb9982017-02-22 16:56:35 +0800[diff] [blame]1/*
2 * Copyright (C) 2016-2017 Rockchip Electronics Co., Ltd
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#ifndef _ASM_ARCH_SDRAM_RK3399_H
8#define _ASM_ARCH_SDRAM_RK3399_H
9
10enum {
11 DDR3 = 0x3,
12 LPDDR2 = 0x5,
13 LPDDR3 = 0x6,
14 LPDDR4 = 0x7,
15 UNUSED = 0xFF
16};
17
18struct rk3399_ddr_pctl_regs {
19 u32 denali_ctl[332];
20};
21
22struct rk3399_ddr_publ_regs {
23 u32 denali_phy[959];
24};
25
26struct rk3399_ddr_pi_regs {
27 u32 denali_pi[200];
28};
29
30struct rk3399_msch_regs {
31 u32 coreid;
32 u32 revisionid;
33 u32 ddrconf;
34 u32 ddrsize;
35 u32 ddrtiminga0;
36 u32 ddrtimingb0;
37 u32 ddrtimingc0;
38 u32 devtodev0;
39 u32 reserved0[(0x110 - 0x20) / 4];
40 u32 ddrmode;
41 u32 reserved1[(0x1000 - 0x114) / 4];
42 u32 agingx0;
43};
44
45struct rk3399_msch_timings {
46 u32 ddrtiminga0;
47 u32 ddrtimingb0;
48 u32 ddrtimingc0;
49 u32 devtodev0;
50 u32 ddrmode;
51 u32 agingx0;
52};
53
54struct rk3399_ddr_cic_regs {
55 u32 cic_ctrl0;
56 u32 cic_ctrl1;
57 u32 cic_idle_th;
58 u32 cic_cg_wait_th;
59 u32 cic_status0;
60 u32 cic_status1;
61 u32 cic_ctrl2;
62 u32 cic_ctrl3;
63 u32 cic_ctrl4;
64};
65
66/* DENALI_CTL_00 */
67#define START 1
68
69/* DENALI_CTL_68 */
70#define PWRUP_SREFRESH_EXIT (1 << 16)
71
72/* DENALI_CTL_274 */
73#define MEM_RST_VALID 1
74
75struct rk3399_sdram_channel {
76 unsigned int rank;
77 /* dram column number, 0 means this channel is invalid */
78 unsigned int col;
79 /* dram bank number, 3:8bank, 2:4bank */
80 unsigned int bk;
81 /* channel buswidth, 2:32bit, 1:16bit, 0:8bit */
82 unsigned int bw;
83 /* die buswidth, 2:32bit, 1:16bit, 0:8bit */
84 unsigned int dbw;
85 /*
86 * row_3_4 = 1: 6Gb or 12Gb die
87 * row_3_4 = 0: normal die, power of 2
88 */
89 unsigned int row_3_4;
90 unsigned int cs0_row;
91 unsigned int cs1_row;
92 unsigned int ddrconfig;
93 struct rk3399_msch_timings noc_timings;
94};
95
96struct rk3399_base_params {
97 unsigned int ddr_freq;
98 unsigned int dramtype;
99 unsigned int num_channels;
100 unsigned int stride;
101 unsigned int odt;
102};
103
104struct rk3399_sdram_params {
105 struct rk3399_sdram_channel ch[2];
106 struct rk3399_base_params base;
107 struct rk3399_ddr_pctl_regs pctl_regs;
108 struct rk3399_ddr_pi_regs pi_regs;
109 struct rk3399_ddr_publ_regs phy_regs;
110};
111
112#define PI_CA_TRAINING (1 << 0)
113#define PI_WRITE_LEVELING (1 << 1)
114#define PI_READ_GATE_TRAINING (1 << 2)
115#define PI_READ_LEVELING (1 << 3)
116#define PI_WDQ_LEVELING (1 << 4)
117#define PI_FULL_TRAINING 0xff
118
119#endif