| Kever Yang | 5db9e67 | 2017-06-23 16:11:05 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2017 Rockchip Electronics Co., Ltd. |
| 3 | * |
| 4 | * SPDX-License-Identifier: GPL-2.0+ |
| 5 | */ |
| 6 | |
| 7 | #ifndef _ASM_ARCH_SDRAM_COMMON_H |
| 8 | #define _ASM_ARCH_SDRAM_COMMON_H |
| 9 | /* |
| 10 | * sys_reg bitfield struct |
| 11 | * [31] row_3_4_ch1 |
| 12 | * [30] row_3_4_ch0 |
| 13 | * [29:28] chinfo |
| 14 | * [27] rank_ch1 |
| 15 | * [26:25] col_ch1 |
| 16 | * [24] bk_ch1 |
| 17 | * [23:22] cs0_row_ch1 |
| 18 | * [21:20] cs1_row_ch1 |
| 19 | * [19:18] bw_ch1 |
| 20 | * [17:16] dbw_ch1; |
| 21 | * [15:13] ddrtype |
| 22 | * [12] channelnum |
| 23 | * [11] rank_ch0 |
| 24 | * [10:9] col_ch0 |
| 25 | * [8] bk_ch0 |
| 26 | * [7:6] cs0_row_ch0 |
| 27 | * [5:4] cs1_row_ch0 |
| 28 | * [3:2] bw_ch0 |
| 29 | * [1:0] dbw_ch0 |
| 30 | */ |
| 31 | #define SYS_REG_DDRTYPE_SHIFT 13 |
| 32 | #define SYS_REG_DDRTYPE_MASK 7 |
| 33 | #define SYS_REG_NUM_CH_SHIFT 12 |
| 34 | #define SYS_REG_NUM_CH_MASK 1 |
| 35 | #define SYS_REG_ROW_3_4_SHIFT(ch) (30 + (ch)) |
| 36 | #define SYS_REG_ROW_3_4_MASK 1 |
| 37 | #define SYS_REG_CHINFO_SHIFT(ch) (28 + (ch)) |
| 38 | #define SYS_REG_RANK_SHIFT(ch) (11 + (ch) * 16) |
| 39 | #define SYS_REG_RANK_MASK 1 |
| 40 | #define SYS_REG_COL_SHIFT(ch) (9 + (ch) * 16) |
| 41 | #define SYS_REG_COL_MASK 3 |
| 42 | #define SYS_REG_BK_SHIFT(ch) (8 + (ch) * 16) |
| 43 | #define SYS_REG_BK_MASK 1 |
| 44 | #define SYS_REG_CS0_ROW_SHIFT(ch) (6 + (ch) * 16) |
| 45 | #define SYS_REG_CS0_ROW_MASK 3 |
| 46 | #define SYS_REG_CS1_ROW_SHIFT(ch) (4 + (ch) * 16) |
| 47 | #define SYS_REG_CS1_ROW_MASK 3 |
| 48 | #define SYS_REG_BW_SHIFT(ch) (2 + (ch) * 16) |
| 49 | #define SYS_REG_BW_MASK 3 |
| 50 | #define SYS_REG_DBW_SHIFT(ch) ((ch) * 16) |
| 51 | #define SYS_REG_DBW_MASK 3 |
| 52 | |
| 53 | /* Get sdram size decode from reg */ |
| 54 | size_t rockchip_sdram_size(phys_addr_t reg); |
| 55 | |
| 56 | /* Called by U-Boot board_init_r for Rockchip SoCs */ |
| 57 | int dram_init(void); |
| 58 | #endif |