blob: ebfc166b4d46810b48a633186e6d3cd9cde9032e [file] [log] [blame]
Peng Fancbe5d382021-08-07 16:01:13 +08001/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright 2020 NXP
4 */
5
6#ifndef __IMX8ULP_EVK_H
7#define __IMX8ULP_EVK_H
8
9#include <linux/sizes.h>
10#include <asm/arch/imx-regs.h>
11
Peng Fancbe5d382021-08-07 16:01:13 +080012#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
Peng Fancbe5d382021-08-07 16:01:13 +080013#define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
14
15#ifdef CONFIG_SPL_BUILD
Peng Fancbe5d382021-08-07 16:01:13 +080016#define CONFIG_MALLOC_F_ADDR 0x22040000
17
Peng Fancbe5d382021-08-07 16:01:13 +080018
19#endif
20
Peng Fancbe5d382021-08-07 16:01:13 +080021/* ENET Config */
22#if defined(CONFIG_FEC_MXC)
Peng Fancbe5d382021-08-07 16:01:13 +080023#define PHY_ANEG_TIMEOUT 20000
24
Peng Fancbe5d382021-08-07 16:01:13 +080025#define CONFIG_FEC_MXC_PHYADDR 1
Peng Fancbe5d382021-08-07 16:01:13 +080026#endif
27
28#ifdef CONFIG_DISTRO_DEFAULTS
29#define BOOT_TARGET_DEVICES(func) \
30 func(MMC, mmc, 0)
31
32#include <config_distro_bootcmd.h>
33#else
34#define BOOTENV
35#endif
36
37/* Initial environment variables */
38#define CONFIG_EXTRA_ENV_SETTINGS \
39 BOOTENV \
Tom Rini9004ee02021-08-23 10:25:30 -040040 "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
41 "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
Peng Fancbe5d382021-08-07 16:01:13 +080042 "image=Image\0" \
43 "console=ttyLP1,115200 earlycon\0" \
44 "fdt_addr_r=0x83000000\0" \
45 "boot_fit=no\0" \
46 "fdtfile=imx8ulp-evk.dtb\0" \
47 "initrd_addr=0x83800000\0" \
48 "bootm_size=0x10000000\0" \
Tom Rinib113bca2021-12-11 14:55:52 -050049 "mmcpart=1\0" \
Peng Fanbb4bb582022-04-15 12:23:41 +080050 "mmcroot=/dev/mmcblk2p2 rootwait rw\0" \
Peng Fancbe5d382021-08-07 16:01:13 +080051
52/* Link Definitions */
Peng Fancbe5d382021-08-07 16:01:13 +080053
54#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
55#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
Peng Fancbe5d382021-08-07 16:01:13 +080056
Peng Fancbe5d382021-08-07 16:01:13 +080057
Peng Fancbe5d382021-08-07 16:01:13 +080058#define CONFIG_SYS_SDRAM_BASE 0x80000000
59#define PHYS_SDRAM 0x80000000
60#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
61
Peng Fancbe5d382021-08-07 16:01:13 +080062/* Using ULP WDOG for reset */
63#define WDOG_BASE_ADDR WDG3_RBASE
64#endif