| Paul Burton | 993ae66 | 2018-12-16 19:25:23 -0300 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | /* |
| 3 | * CI20 configuration |
| 4 | * |
| 5 | * Copyright (c) 2013 Imagination Technologies |
| 6 | * Author: Paul Burton <paul.burton@imgtec.com> |
| 7 | */ |
| 8 | |
| 9 | #ifndef __CONFIG_CI20_H__ |
| 10 | #define __CONFIG_CI20_H__ |
| 11 | |
| Paul Burton | 993ae66 | 2018-12-16 19:25:23 -0300 | [diff] [blame] | 12 | /* Ingenic JZ4780 clock configuration. */ |
| Paul Burton | 993ae66 | 2018-12-16 19:25:23 -0300 | [diff] [blame] | 13 | #define CONFIG_SYS_MHZ 1200 |
| 14 | #define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000) |
| 15 | |
| 16 | /* Memory configuration */ |
| 17 | #define CONFIG_SYS_MONITOR_LEN (512 * 1024) |
| Paul Burton | 993ae66 | 2018-12-16 19:25:23 -0300 | [diff] [blame] | 18 | |
| 19 | #define CONFIG_SYS_SDRAM_BASE 0x80000000 /* cached (KSEG0) address */ |
| 20 | #define CONFIG_SYS_INIT_SP_OFFSET 0x400000 |
| Paul Burton | 993ae66 | 2018-12-16 19:25:23 -0300 | [diff] [blame] | 21 | |
| Paul Burton | 993ae66 | 2018-12-16 19:25:23 -0300 | [diff] [blame] | 22 | /* NS16550-ish UARTs */ |
| 23 | #define CONFIG_SYS_NS16550_CLK 48000000 |
| Paul Burton | 993ae66 | 2018-12-16 19:25:23 -0300 | [diff] [blame] | 24 | |
| 25 | /* Ethernet: davicom DM9000 */ |
| Paul Burton | 993ae66 | 2018-12-16 19:25:23 -0300 | [diff] [blame] | 26 | #define CONFIG_DM9000_BASE 0xb6000000 |
| 27 | #define DM9000_IO CONFIG_DM9000_BASE |
| 28 | #define DM9000_DATA (CONFIG_DM9000_BASE + 2) |
| 29 | |
| Paul Burton | 993ae66 | 2018-12-16 19:25:23 -0300 | [diff] [blame] | 30 | /* Miscellaneous configuration options */ |
| Paul Burton | 993ae66 | 2018-12-16 19:25:23 -0300 | [diff] [blame] | 31 | |
| Paul Burton | 993ae66 | 2018-12-16 19:25:23 -0300 | [diff] [blame] | 32 | #endif /* __CONFIG_CI20_H__ */ |