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git01.mediatek.com / filogic / uboot / 3b829a2c0bac0f9767988942751eaac8e3ade5e0 / . / dts / upstream / src / arm64 / freescale / imx8mp-debix-som-a-bmb-08.dts
blob: b11d694b98e1bc6818b40ca48f8d5bee2fd090c5 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2019 NXP
4 * Copyright (C) 2023 Pengutronix, Marco Felsch <kernel@pengutronix.de>
5 */
6
7/dts-v1/;
8
9#include "imx8mp-debix-som-a.dtsi"
10
11/ {
12 model = "Polyhex i.MX8MPlus Debix SOM A on BMB-08";
13 compatible = "polyhex,imx8mp-debix-som-a-bmb-08", "polyhex,imx8mp-debix-som-a",
14 "fsl,imx8mp";
15
16 aliases {
17 ethernet0 = &eqos;
18 ethernet1 = &fec;
19 };
20
21 chosen {
22 stdout-path = &uart2;
23 };
24
25 reg_baseboard_vdd3v3: regulator-baseboard-vdd3v3 {
26 compatible = "regulator-fixed";
27 regulator-min-microvolt = <3300000>;
28 regulator-max-microvolt = <3300000>;
29 regulator-name = "BB_VDD3V3";
30 /* Required timings for ethernet phy's */
31 startup-delay-us = <50000>;
32 off-on-delay-us = <110000>;
33 gpio = <&expander0 10 GPIO_ACTIVE_HIGH>;
34 enable-active-high;
35 };
36
37 reg_baseboard_vdd5v0: regulator-baseboard-vdd5v0 {
38 compatible = "regulator-fixed";
39 regulator-min-microvolt = <5000000>;
40 regulator-max-microvolt = <5000000>;
41 regulator-name = "BB_VDD5V";
42 gpio = <&expander0 9 GPIO_ACTIVE_HIGH>;
43 enable-active-high;
44 };
45
46 regulator-som-vdd1v8 {
47 compatible = "regulator-fixed";
48 regulator-min-microvolt = <1800000>;
49 regulator-max-microvolt = <1800000>;
50 regulator-name = "SOM_VDD1V8_SW";
51 gpio = <&expander0 12 GPIO_ACTIVE_HIGH>;
52 enable-active-high;
53 regulator-always-on;
54 };
55
56 regulator-som-vdd3v3 {
57 compatible = "regulator-fixed";
58 regulator-min-microvolt = <3300000>;
59 regulator-max-microvolt = <3300000>;
60 regulator-name = "SOM_VDD3V3_SW";
61 gpio = <&expander0 11 GPIO_ACTIVE_HIGH>;
62 enable-active-high;
63 regulator-always-on;
64 };
65
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]66 reg_csi1_1v8: regulator-csi1-vdd1v8 {
67 compatible = "regulator-fixed";
68 regulator-min-microvolt = <1800000>;
69 regulator-max-microvolt = <1800000>;
70 regulator-name = "CSI1_VDD1V8";
71 gpio = <&expander0 13 GPIO_ACTIVE_HIGH>;
72 enable-active-high;
73 vin-supply = <&reg_baseboard_vdd3v3>;
74 };
75
76 reg_csi1_3v3: regulator-csi1-vdd3v3 {
77 compatible = "regulator-fixed";
78 regulator-min-microvolt = <3300000>;
79 regulator-max-microvolt = <3300000>;
80 regulator-name = "CSI1_VDD3V3";
81 gpio = <&expander0 14 GPIO_ACTIVE_HIGH>;
82 enable-active-high;
83 vin-supply = <&reg_vdd5v0>;
84 };
85
86 reg_csi2_1v8: regulator-csi2-vdd1v8 {
87 compatible = "regulator-fixed";
88 pinctrl-names = "default";
89 pinctrl-0 = <&pinctrl_reg_csi2_1v8>;
90 regulator-min-microvolt = <1800000>;
91 regulator-max-microvolt = <1800000>;
92 regulator-name = "CSI2_VDD1V8";
93 gpio = <&gpio3 21 GPIO_ACTIVE_HIGH>;
94 enable-active-high;
95 vin-supply = <&reg_baseboard_vdd3v3>;
96 };
97
98 reg_csi2_3v3: regulator-csi2-vdd3v3 {
99 compatible = "regulator-fixed";
100 pinctrl-names = "default";
101 pinctrl-0 = <&pinctrl_reg_csi2_3v3>;
102 regulator-min-microvolt = <3300000>;
103 regulator-max-microvolt = <3300000>;
104 regulator-name = "CSI2_VDD3V3";
105 gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>;
106 enable-active-high;
107 vin-supply = <&reg_vdd5v0>;
108 };
109
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]110 regulator-vbus-usb20 {
111 compatible = "regulator-fixed";
112 regulator-min-microvolt = <5000000>;
113 regulator-max-microvolt = <5000000>;
114 regulator-name = "USB20_5V";
115 gpio = <&expander1 14 GPIO_ACTIVE_HIGH>;
116 enable-active-high;
117 regulator-always-on;
118 vin-supply = <&reg_baseboard_vdd5v0>;
119 };
120
121 regulator-vbus-usb30 {
122 compatible = "regulator-fixed";
123 regulator-min-microvolt = <5000000>;
124 regulator-max-microvolt = <5000000>;
125 regulator-name = "USB30_5V";
126 gpio = <&expander1 12 GPIO_ACTIVE_HIGH>;
127 enable-active-high;
128 regulator-always-on;
129 vin-supply = <&reg_baseboard_vdd5v0>;
130 };
131
132 reg_vdd5v0: regulator-vdd5v0 {
133 compatible = "regulator-fixed";
134 regulator-min-microvolt = <5000000>;
135 regulator-max-microvolt = <5000000>;
136 regulator-name = "VDD_5V";
137 gpio = <&expander0 8 GPIO_ACTIVE_HIGH>;
138 enable-active-high;
139 };
140};
141
142&eqos {
143 pinctrl-names = "default";
144 pinctrl-0 = <&pinctrl_eqos>;
145 nvmem-cells = <&ethmac1>;
146 nvmem-cell-names = "mac-address";
147 phy-supply = <&reg_baseboard_vdd3v3>;
148 phy-handle = <&ethphy0>;
149 phy-mode = "rgmii-id";
150 status = "okay";
151
152 mdio {
153 compatible = "snps,dwmac-mdio";
154 #address-cells = <1>;
155 #size-cells = <0>;
156
157 ethphy0: ethernet-phy@1 {
158 compatible = "ethernet-phy-ieee802.3-c22";
159 reg = <1>;
160 reset-gpios = <&gpio4 18 GPIO_ACTIVE_LOW>;
161 reset-assert-us = <20000>;
162 reset-deassert-us = <150000>;
163 eee-broken-1000t;
164 realtek,clkout-disable;
165 };
166 };
167};
168
169&fec {
170 pinctrl-names = "default";
171 pinctrl-0 = <&pinctrl_fec>;
172 nvmem-cells = <&ethmac2>;
173 nvmem-cell-names = "mac-address";
174 phy-supply = <&reg_baseboard_vdd3v3>;
175 phy-handle = <&ethphy1>;
176 phy-mode = "rgmii-id";
177 fsl,magic-packet;
178 status = "okay";
179
180 mdio {
181 #address-cells = <1>;
182 #size-cells = <0>;
183
184 ethphy1: ethernet-phy@1 {
185 compatible = "ethernet-phy-ieee802.3-c22";
186 reg = <1>;
187 reset-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
188 reset-assert-us = <20000>;
189 reset-deassert-us = <150000>;
190 eee-broken-1000t;
191 realtek,clkout-disable;
192 };
193 };
194};
195
196&flexcan1 {
197 pinctrl-names = "default";
198 pinctrl-0 = <&pinctrl_flexcan1>;
199 xceiver-supply = <&reg_vdd5v0>;
200 status = "okay";
201};
202
203&flexcan2 {
204 pinctrl-names = "default";
205 pinctrl-0 = <&pinctrl_flexcan2>;
206 xceiver-supply = <&reg_vdd5v0>;
207 status = "okay";
208};
209
210&flexspi {
211 pinctrl-names = "default";
212 pinctrl-0 = <&pinctrl_flexspi0>;
213 status = "okay";
214
215 flash: flash@0 {
216 compatible = "jedec,spi-nor";
217 reg = <0>;
218 spi-max-frequency = <80000000>;
219 spi-tx-bus-width = <1>;
220 spi-rx-bus-width = <4>;
221 #address-cells = <1>;
222 #size-cells = <1>;
223 };
224};
225
226&i2c4 {
227 expander0: gpio@20 {
228 compatible = "nxp,pca9535";
229 reg = <0x20>;
230 gpio-controller;
231 #gpio-cells = <0x02>;
232 };
233
234 expander1: gpio@23 {
235 compatible = "nxp,pca9535";
236 reg = <0x23>;
237 gpio-controller;
238 #gpio-cells = <0x02>;
239
240 /*
241 * Since USB1 is bound to peripheral mode we need to ensure
242 * that VBUS is turned off.
243 */
244 usb30-otg-hog {
245 gpio-hog;
246 gpios = <13 GPIO_ACTIVE_HIGH>;
247 output-low;
248 line-name = "USB30_OTG_EN";
249 };
250 };
251
252 rtc@51 {
253 compatible = "haoyu,hym8563";
254 reg = <0x51>;
255 pinctrl-names = "default";
256 pinctrl-0 = <&pinctrl_rtc>;
257 interrupt-parent = <&gpio4>;
258 interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
259 #clock-cells = <0>;
260 };
261
262 eeprom@52 {
263 compatible = "atmel,24c02";
264 reg = <0x52>;
265 pagesize = <16>;
266 #address-cells = <1>;
267 #size-cells = <1>;
268
269 /* MACs stored in ASCII */
270 ethmac1: mac-address@0 {
271 reg = <0x0 0xc>;
272 };
273
274 ethmac2: mac-address@c {
275 reg = <0xc 0xc>;
276 };
277 };
278};
279
280&snvs_pwrkey {
281 status = "okay";
282};
283
284/* Debug */
285&uart2 {
286 pinctrl-names = "default";
287 pinctrl-0 = <&pinctrl_uart2>;
288 status = "okay";
289};
290
291&uart3 {
292 pinctrl-names = "default";
293 pinctrl-0 = <&pinctrl_uart3>;
294 status = "okay";
295};
296
297&uart4 {
298 pinctrl-names = "default";
299 pinctrl-0 = <&pinctrl_uart4>;
300 status = "okay";
301};
302
303&usb3_0 {
304 status = "okay";
305};
306
307&usb3_1 {
308 status = "okay";
309};
310
311&usb_dwc3_0 {
312 dr_mode = "peripheral";
313 status = "okay";
314};
315
316&usb_dwc3_1 {
317 dr_mode = "host";
318 #address-cells = <1>;
319 #size-cells = <0>;
320 status = "okay";
321
322 /* 2.x hub on port 1 */
323 usb_hub_2_x: hub@1 {
324 compatible = "usb5e3,610";
325 reg = <1>;
326 reset-gpios = <&expander1 9 GPIO_ACTIVE_LOW>;
327 vdd-supply = <&reg_vdd5v0>;
328 peer-hub = <&usb_hub_3_x>;
329 };
330
331 /* 3.x hub on port 2 */
332 usb_hub_3_x: hub@2 {
333 compatible = "usb5e3,620";
334 reg = <2>;
335 reset-gpios = <&expander1 9 GPIO_ACTIVE_LOW>;
336 vdd-supply = <&reg_vdd5v0>;
337 peer-hub = <&usb_hub_2_x>;
338 };
339};
340
341&usb3_phy0 {
342 status = "okay";
343};
344
345&usb3_phy1 {
346 status = "okay";
347};
348
349/* µSD Card */
350&usdhc2 {
351 pinctrl-names = "default", "state_100mhz", "state_200mhz";
352 pinctrl-0 = <&pinctrl_usdhc2>;
353 pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
354 pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
355 assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
356 assigned-clock-rates = <400000000>;
357 vmmc-supply = <&reg_usdhc2_vmmc>;
358 bus-width = <4>;
359 disable-wp;
360 no-sdio;
361 no-mmc;
362 status = "okay";
363};
364
365&iomuxc {
366 pinctrl_eqos: eqosgrp {
367 fsl,pins = <
368 MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3
369 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3
370 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91
371 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91
372 MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91
373 MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91
374 MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91
375 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91
376 MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f
377 MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f
378 MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f
379 MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f
380 MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f
381 MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f
382
383 MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN 0x1f
384 MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x19
385 >;
386 };
387
388 pinctrl_fec: fecgrp {
389 fsl,pins = <
390 MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3
391 MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3
392 MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91
393 MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91
394 MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91
395 MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91
396 MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91
397 MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91
398 MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f
399 MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f
400 MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f
401 MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f
402 MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f
403 MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f
404 MX8MP_IOMUXC_SAI1_RXD0__ENET1_1588_EVENT1_IN 0x1f
405 MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x19
406 >;
407 };
408
409 pinctrl_flexcan1: flexcan1grp {
410 fsl,pins = <
411 MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX 0x154
412 MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX 0x154
413 >;
414 };
415
416 pinctrl_flexcan2: flexcan2grp {
417 fsl,pins = <
418 MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154
419 MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154
420 >;
421 };
422
423 pinctrl_flexspi0: flexspi0grp {
424 fsl,pins = <
425 MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2
426 MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82
427 MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82
428 MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82
429 MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82
430 MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82
431 >;
432 };
433
434 pinctrl_i2c1: i2c1grp {
435 fsl,pins = <
436 MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2
437 MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2
438 >;
439 };
440
441 pinctrl_i2c4: i2c4grp {
442 fsl,pins = <
443 MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3
444 MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3
445 >;
446 };
447
448 pinctrl_rtc: rtcgrp {
449 fsl,pins = <
450 MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x140
451 >;
452 };
453
454 pinctrl_pmic: pmicgrp {
455 fsl,pins = <
456 MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41
457 >;
458 };
459
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]460 pinctrl_reg_csi2_1v8: regcsi21v8grp {
461 fsl,pins = <
462 MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x19
463 >;
464 };
465
466 pinctrl_reg_csi2_3v3: regcsi23v3grp {
467 fsl,pins = <
468 MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 0x19
469 >;
470 };
471
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]472 pinctrl_uart2: uart2grp {
473 fsl,pins = <
474 MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x14f
475 MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x14f
476 >;
477 };
478
479 pinctrl_uart3: uart3grp {
480 fsl,pins = <
481 MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x49
482 MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x49
483 >;
484 };
485
486 pinctrl_uart4: uart4grp {
487 fsl,pins = <
488 MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x49
489 MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x49
490 >;
491 };
492
493 pinctrl_usdhc2: usdhc2grp {
494 fsl,pins = <
495 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
496 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
497 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
498 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
499 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
500 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
501 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
502 >;
503 };
504
505 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
506 fsl,pins = <
507 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
508 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
509 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
510 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
511 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
512 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
513 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
514 >;
515 };
516
517 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
518 fsl,pins = <
519 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
520 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
521 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
522 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
523 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
524 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
525 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
526 >;
527 };
528};