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git01.mediatek.com / filogic / uboot / 3b829a2c0bac0f9767988942751eaac8e3ade5e0 / . / dts / upstream / src / arm / ti / keystone / keystone-clocks.dtsi
blob: 0397c3423d2db5d5ea4b9300565274b103565816 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for Keystone 2 clock tree
4 *
5 * Copyright (C) 2013-2017 Texas Instruments Incorporated - http://www.ti.com/
6 */
7
8clocks {
9 #address-cells = <1>;
10 #size-cells = <1>;
11 ranges;
12
13 mainmuxclk: mainmuxclk@2310108 {
14 #clock-cells = <0>;
15 compatible = "ti,keystone,pll-mux-clock";
16 clocks = <&mainpllclk>, <&refclksys>;
17 reg = <0x02310108 4>;
18 bit-shift = <23>;
19 bit-mask = <1>;
20 clock-output-names = "mainmuxclk";
21 };
22
23 chipclk1: chipclk1 {
24 #clock-cells = <0>;
25 compatible = "fixed-factor-clock";
26 clocks = <&mainmuxclk>;
27 clock-div = <1>;
28 clock-mult = <1>;
29 clock-output-names = "chipclk1";
30 };
31
32 chipclk1rstiso: chipclk1rstiso {
33 #clock-cells = <0>;
34 compatible = "fixed-factor-clock";
35 clocks = <&mainmuxclk>;
36 clock-div = <1>;
37 clock-mult = <1>;
38 clock-output-names = "chipclk1rstiso";
39 };
40
41 gemtraceclk: gemtraceclk@2310120 {
42 #clock-cells = <0>;
43 compatible = "ti,keystone,pll-divider-clock";
44 clocks = <&mainmuxclk>;
45 reg = <0x02310120 4>;
46 bit-shift = <0>;
47 bit-mask = <8>;
48 clock-output-names = "gemtraceclk";
49 };
50
51 chipstmxptclk: chipstmxptclk@2310164 {
52 #clock-cells = <0>;
53 compatible = "ti,keystone,pll-divider-clock";
54 clocks = <&mainmuxclk>;
55 reg = <0x02310164 4>;
56 bit-shift = <0>;
57 bit-mask = <8>;
58 clock-output-names = "chipstmxptclk";
59 };
60
61 chipclk12: chipclk12 {
62 #clock-cells = <0>;
63 compatible = "fixed-factor-clock";
64 clocks = <&chipclk1>;
65 clock-div = <2>;
66 clock-mult = <1>;
67 clock-output-names = "chipclk12";
68 };
69
70 chipclk13: chipclk13 {
71 #clock-cells = <0>;
72 compatible = "fixed-factor-clock";
73 clocks = <&chipclk1>;
74 clock-div = <3>;
75 clock-mult = <1>;
76 clock-output-names = "chipclk13";
77 };
78
79 paclk13: paclk13 {
80 #clock-cells = <0>;
81 compatible = "fixed-factor-clock";
82 clocks = <&papllclk>;
83 clock-div = <3>;
84 clock-mult = <1>;
85 clock-output-names = "paclk13";
86 };
87
88 chipclk14: chipclk14 {
89 #clock-cells = <0>;
90 compatible = "fixed-factor-clock";
91 clocks = <&chipclk1>;
92 clock-div = <4>;
93 clock-mult = <1>;
94 clock-output-names = "chipclk14";
95 };
96
97 chipclk16: chipclk16 {
98 #clock-cells = <0>;
99 compatible = "fixed-factor-clock";
100 clocks = <&chipclk1>;
101 clock-div = <6>;
102 clock-mult = <1>;
103 clock-output-names = "chipclk16";
104 };
105
106 chipclk112: chipclk112 {
107 #clock-cells = <0>;
108 compatible = "fixed-factor-clock";
109 clocks = <&chipclk1>;
110 clock-div = <12>;
111 clock-mult = <1>;
112 clock-output-names = "chipclk112";
113 };
114
115 chipclk124: chipclk124 {
116 #clock-cells = <0>;
117 compatible = "fixed-factor-clock";
118 clocks = <&chipclk1>;
119 clock-div = <24>;
120 clock-mult = <1>;
121 clock-output-names = "chipclk114";
122 };
123
124 chipclk1rstiso13: chipclk1rstiso13 {
125 #clock-cells = <0>;
126 compatible = "fixed-factor-clock";
127 clocks = <&chipclk1rstiso>;
128 clock-div = <3>;
129 clock-mult = <1>;
130 clock-output-names = "chipclk1rstiso13";
131 };
132
133 chipclk1rstiso14: chipclk1rstiso14 {
134 #clock-cells = <0>;
135 compatible = "fixed-factor-clock";
136 clocks = <&chipclk1rstiso>;
137 clock-div = <4>;
138 clock-mult = <1>;
139 clock-output-names = "chipclk1rstiso14";
140 };
141
142 chipclk1rstiso16: chipclk1rstiso16 {
143 #clock-cells = <0>;
144 compatible = "fixed-factor-clock";
145 clocks = <&chipclk1rstiso>;
146 clock-div = <6>;
147 clock-mult = <1>;
148 clock-output-names = "chipclk1rstiso16";
149 };
150
151 chipclk1rstiso112: chipclk1rstiso112 {
152 #clock-cells = <0>;
153 compatible = "fixed-factor-clock";
154 clocks = <&chipclk1rstiso>;
155 clock-div = <12>;
156 clock-mult = <1>;
157 clock-output-names = "chipclk1rstiso112";
158 };
159
160 clkmodrst0: clkmodrst0@2350000 {
161 #clock-cells = <0>;
162 compatible = "ti,keystone,psc-clock";
163 clocks = <&chipclk16>;
164 clock-output-names = "modrst0";
165 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
166 reg-names = "control", "domain";
167 domain-id = <0>;
168 };
169
170
171 clkusb: clkusb@2350008 {
172 #clock-cells = <0>;
173 compatible = "ti,keystone,psc-clock";
174 clocks = <&chipclk16>;
175 clock-output-names = "usb";
176 reg = <0x02350008 0xb00>, <0x02350000 0x400>;
177 reg-names = "control", "domain";
178 domain-id = <0>;
179 };
180
181 clkaemifspi: clkaemifspi@235000c {
182 #clock-cells = <0>;
183 compatible = "ti,keystone,psc-clock";
184 clocks = <&chipclk16>;
185 clock-output-names = "aemif-spi";
186 reg = <0x0235000c 0xb00>, <0x02350000 0x400>;
187 reg-names = "control", "domain";
188 domain-id = <0>;
189 };
190
191
192 clkdebugsstrc: clkdebugsstrc@2350014 {
193 #clock-cells = <0>;
194 compatible = "ti,keystone,psc-clock";
195 clocks = <&chipclk13>;
196 clock-output-names = "debugss-trc";
197 reg = <0x02350014 0xb00>, <0x02350000 0x400>;
198 reg-names = "control", "domain";
199 domain-id = <1>;
200 };
201
202 clktetbtrc: clktetbtrc@2350018 {
203 #clock-cells = <0>;
204 compatible = "ti,keystone,psc-clock";
205 clocks = <&chipclk13>;
206 clock-output-names = "tetb-trc";
207 reg = <0x02350018 0xb00>, <0x02350004 0x400>;
208 reg-names = "control", "domain";
209 domain-id = <1>;
210 };
211
212 clkpa: clkpa@235001c {
213 #clock-cells = <0>;
214 compatible = "ti,keystone,psc-clock";
215 clocks = <&paclk13>;
216 clock-output-names = "pa";
217 reg = <0x0235001c 0xb00>, <0x02350008 0x400>;
218 reg-names = "control", "domain";
219 domain-id = <2>;
220 };
221
222 clkcpgmac: clkcpgmac@2350020 {
223 #clock-cells = <0>;
224 compatible = "ti,keystone,psc-clock";
225 clocks = <&clkpa>;
226 clock-output-names = "cpgmac";
227 reg = <0x02350020 0xb00>, <0x02350008 0x400>;
228 reg-names = "control", "domain";
229 domain-id = <2>;
230 };
231
232 clksa: clksa@2350024 {
233 #clock-cells = <0>;
234 compatible = "ti,keystone,psc-clock";
235 clocks = <&clkpa>;
236 clock-output-names = "sa";
237 reg = <0x02350024 0xb00>, <0x02350008 0x400>;
238 reg-names = "control", "domain";
239 domain-id = <2>;
240 };
241
242 clkpcie: clkpcie@2350028 {
243 #clock-cells = <0>;
244 compatible = "ti,keystone,psc-clock";
245 clocks = <&chipclk12>;
246 clock-output-names = "pcie";
247 reg = <0x02350028 0xb00>, <0x0235000c 0x400>;
248 reg-names = "control", "domain";
249 domain-id = <3>;
250 };
251
252 clksr: clksr@2350034 {
253 #clock-cells = <0>;
254 compatible = "ti,keystone,psc-clock";
255 clocks = <&chipclk1rstiso112>;
256 clock-output-names = "sr";
257 reg = <0x02350034 0xb00>, <0x02350018 0x400>;
258 reg-names = "control", "domain";
259 domain-id = <6>;
260 };
261
262 clkgem0: clkgem0@235003c {
263 #clock-cells = <0>;
264 compatible = "ti,keystone,psc-clock";
265 clocks = <&chipclk1>;
266 clock-output-names = "gem0";
267 reg = <0x0235003c 0xb00>, <0x02350020 0x400>;
268 reg-names = "control", "domain";
269 domain-id = <8>;
270 };
271
272 clkddr30: clkddr30@235005c {
273 #clock-cells = <0>;
274 compatible = "ti,keystone,psc-clock";
275 clocks = <&chipclk12>;
276 clock-output-names = "ddr3-0";
277 reg = <0x0235005c 0xb00>, <0x02350040 0x400>;
278 reg-names = "control", "domain";
279 domain-id = <16>;
280 };
281
282 clkwdtimer0: clkwdtimer0@2350000 {
283 #clock-cells = <0>;
284 compatible = "ti,keystone,psc-clock";
285 clocks = <&clkmodrst0>;
286 clock-output-names = "timer0";
287 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
288 reg-names = "control", "domain";
289 domain-id = <0>;
290 };
291
292 clkwdtimer1: clkwdtimer1@2350000 {
293 #clock-cells = <0>;
294 compatible = "ti,keystone,psc-clock";
295 clocks = <&clkmodrst0>;
296 clock-output-names = "timer1";
297 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
298 reg-names = "control", "domain";
299 domain-id = <0>;
300 };
301
302 clkwdtimer2: clkwdtimer2@2350000 {
303 #clock-cells = <0>;
304 compatible = "ti,keystone,psc-clock";
305 clocks = <&clkmodrst0>;
306 clock-output-names = "timer2";
307 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
308 reg-names = "control", "domain";
309 domain-id = <0>;
310 };
311
312 clkwdtimer3: clkwdtimer3@2350000 {
313 #clock-cells = <0>;
314 compatible = "ti,keystone,psc-clock";
315 clocks = <&clkmodrst0>;
316 clock-output-names = "timer3";
317 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
318 reg-names = "control", "domain";
319 domain-id = <0>;
320 };
321
322 clktimer15: clktimer15@2350000 {
323 #clock-cells = <0>;
324 compatible = "ti,keystone,psc-clock";
325 clocks = <&clkmodrst0>;
326 clock-output-names = "timer15";
327 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
328 reg-names = "control", "domain";
329 domain-id = <0>;
330 };
331
332 clkuart0: clkuart0@2350000 {
333 #clock-cells = <0>;
334 compatible = "ti,keystone,psc-clock";
335 clocks = <&clkmodrst0>;
336 clock-output-names = "uart0";
337 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
338 reg-names = "control", "domain";
339 domain-id = <0>;
340 };
341
342 clkuart1: clkuart1@2350000 {
343 #clock-cells = <0>;
344 compatible = "ti,keystone,psc-clock";
345 clocks = <&clkmodrst0>;
346 clock-output-names = "uart1";
347 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
348 reg-names = "control", "domain";
349 domain-id = <0>;
350 };
351
352 clkaemif: clkaemif@2350000 {
353 #clock-cells = <0>;
354 compatible = "ti,keystone,psc-clock";
355 clocks = <&clkaemifspi>;
356 clock-output-names = "aemif";
357 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
358 reg-names = "control", "domain";
359 domain-id = <0>;
360 };
361
362 clkusim: clkusim@2350000 {
363 #clock-cells = <0>;
364 compatible = "ti,keystone,psc-clock";
365 clocks = <&clkmodrst0>;
366 clock-output-names = "usim";
367 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
368 reg-names = "control", "domain";
369 domain-id = <0>;
370 };
371
372 clki2c: clki2c@2350000 {
373 #clock-cells = <0>;
374 compatible = "ti,keystone,psc-clock";
375 clocks = <&clkmodrst0>;
376 clock-output-names = "i2c";
377 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
378 reg-names = "control", "domain";
379 domain-id = <0>;
380 };
381
382 clkspi: clkspi@2350000 {
383 #clock-cells = <0>;
384 compatible = "ti,keystone,psc-clock";
385 clocks = <&clkaemifspi>;
386 clock-output-names = "spi";
387 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
388 reg-names = "control", "domain";
389 domain-id = <0>;
390 };
391
392 clkgpio: clkgpio@2350000 {
393 #clock-cells = <0>;
394 compatible = "ti,keystone,psc-clock";
395 clocks = <&clkmodrst0>;
396 clock-output-names = "gpio";
397 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
398 reg-names = "control", "domain";
399 domain-id = <0>;
400 };
401
402 clkkeymgr: clkkeymgr@2350000 {
403 #clock-cells = <0>;
404 compatible = "ti,keystone,psc-clock";
405 clocks = <&clkmodrst0>;
406 clock-output-names = "keymgr";
407 reg = <0x02350000 0xb00>, <0x02350000 0x400>;
408 reg-names = "control", "domain";
409 domain-id = <0>;
410 };
411
412 /*
413 * Below are set of fixed, input clocks definitions,
414 * for which real frequencies have to be defined in board files.
415 * Those clocks can be used as reference clocks for some HW modules
416 * (as cpts, for example) by configuring corresponding clock muxes.
417 */
418 timi0: timi0 {
419 #clock-cells = <0>;
420 compatible = "fixed-clock";
421 clock-frequency = <0>;
422 clock-output-names = "timi0";
423 };
424
425 timi1: timi1 {
426 #clock-cells = <0>;
427 compatible = "fixed-clock";
428 clock-frequency = <0>;
429 clock-output-names = "timi1";
430 };
431
432 tsrefclk: tsrefclk {
433 #clock-cells = <0>;
434 compatible = "fixed-clock";
435 clock-frequency = <0>;
436 clock-output-names = "tsrefclk";
437 };
438};