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git01.mediatek.com / filogic / uboot / 3b829a2c0bac0f9767988942751eaac8e3ade5e0 / . / dts / upstream / src / arm / rockchip / rv1126-sonoff-ihost.dtsi
blob: 32b329e87a0cd3f880d123c832c265d54b9b1b4c [file] [log] [blame]
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
4 * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
5 */
6
7/ {
8 aliases {
9 ethernet0 = &gmac;
10 mmc0 = &emmc;
11 };
12
13 chosen {
14 stdout-path = "serial2:1500000n8";
15 };
16
17 vcc5v0_sys: regulator-vcc5v0-sys {
18 compatible = "regulator-fixed";
19 regulator-name = "vcc5v0_sys";
20 regulator-always-on;
21 regulator-boot-on;
22 regulator-min-microvolt = <5000000>;
23 regulator-max-microvolt = <5000000>;
24 };
25
26 sdio_pwrseq: pwrseq-sdio {
27 compatible = "mmc-pwrseq-simple";
28 clocks = <&rk809 1>;
29 clock-names = "ext_clock";
30 pinctrl-names = "default";
31 pinctrl-0 = <&wifi_enable_h>;
32 reset-gpios = <&gpio1 RK_PD0 GPIO_ACTIVE_LOW>;
33 };
34};
35
36&emmc {
37 bus-width = <8>;
38 cap-mmc-highspeed;
39 mmc-hs200-1_8v;
40 non-removable;
41 pinctrl-names = "default";
42 pinctrl-0 = <&emmc_bus8 &emmc_cmd &emmc_clk &emmc_rstnout>;
43 rockchip,default-sample-phase = <90>;
44 vmmc-supply = <&vcc_3v3>;
45 vqmmc-supply = <&vcc_1v8>;
46 status = "okay";
47};
48
49&i2c0 {
50 clock-frequency = <400000>;
51 status = "okay";
52
53 rk809: pmic@20 {
54 compatible = "rockchip,rk809";
55 reg = <0x20>;
56 interrupt-parent = <&gpio0>;
57 interrupts = <RK_PB1 IRQ_TYPE_LEVEL_LOW>;
58 #clock-cells = <1>;
59 clock-output-names = "rk808-clkout1", "rk808-clkout2";
60 pinctrl-names = "default";
61 pinctrl-0 = <&pmic_int_l>;
62 rockchip,system-power-controller;
63 wakeup-source;
64
65 vcc1-supply = <&vcc5v0_sys>;
66 vcc2-supply = <&vcc5v0_sys>;
67 vcc3-supply = <&vcc5v0_sys>;
68 vcc4-supply = <&vcc5v0_sys>;
69 vcc5-supply = <&vcc_buck5>;
70 vcc6-supply = <&vcc_buck5>;
71 vcc7-supply = <&vcc5v0_sys>;
72 vcc8-supply = <&vcc3v3_sys>;
73 vcc9-supply = <&vcc5v0_sys>;
74
75 regulators {
76 vdd_npu_vepu: DCDC_REG1 {
77 regulator-name = "vdd_npu_vepu";
78 regulator-always-on;
79 regulator-boot-on;
80 regulator-initial-mode = <0x2>;
81 regulator-min-microvolt = <650000>;
82 regulator-max-microvolt = <950000>;
83 regulator-ramp-delay = <6001>;
84 regulator-state-mem {
85 regulator-off-in-suspend;
86 };
87 };
88
89 vdd_arm: DCDC_REG2 {
90 regulator-name = "vdd_arm";
91 regulator-always-on;
92 regulator-boot-on;
93 regulator-initial-mode = <0x2>;
94 regulator-min-microvolt = <725000>;
95 regulator-max-microvolt = <1350000>;
96 regulator-ramp-delay = <6001>;
97 regulator-state-mem {
98 regulator-off-in-suspend;
99 };
100 };
101
102 vcc_ddr: DCDC_REG3 {
103 regulator-name = "vcc_ddr";
104 regulator-always-on;
105 regulator-boot-on;
106 regulator-initial-mode = <0x2>;
107 regulator-state-mem {
108 regulator-on-in-suspend;
109 };
110 };
111
112 vcc3v3_sys: DCDC_REG4 {
113 regulator-name = "vcc3v3_sys";
114 regulator-always-on;
115 regulator-boot-on;
116 regulator-initial-mode = <0x2>;
117 regulator-min-microvolt = <3300000>;
118 regulator-max-microvolt = <3300000>;
119 regulator-state-mem {
120 regulator-on-in-suspend;
121 regulator-suspend-microvolt = <3300000>;
122 };
123 };
124
125 vcc_buck5: DCDC_REG5 {
126 regulator-name = "vcc_buck5";
127 regulator-always-on;
128 regulator-boot-on;
129 regulator-min-microvolt = <2200000>;
130 regulator-max-microvolt = <2200000>;
131 regulator-state-mem {
132 regulator-on-in-suspend;
133 regulator-suspend-microvolt = <2200000>;
134 };
135 };
136
137 vcc_0v8: LDO_REG1 {
138 regulator-name = "vcc_0v8";
139 regulator-always-on;
140 regulator-boot-on;
141 regulator-min-microvolt = <800000>;
142 regulator-max-microvolt = <800000>;
143 regulator-state-mem {
144 regulator-off-in-suspend;
145 };
146 };
147
148 vcc1v8_pmu: LDO_REG2 {
149 regulator-name = "vcc1v8_pmu";
150 regulator-always-on;
151 regulator-boot-on;
152 regulator-min-microvolt = <1800000>;
153 regulator-max-microvolt = <1800000>;
154 regulator-state-mem {
155 regulator-on-in-suspend;
156 regulator-suspend-microvolt = <1800000>;
157 };
158 };
159
160 vdd0v8_pmu: LDO_REG3 {
161 regulator-name = "vcc0v8_pmu";
162 regulator-always-on;
163 regulator-boot-on;
164 regulator-min-microvolt = <800000>;
165 regulator-max-microvolt = <800000>;
166 regulator-state-mem {
167 regulator-on-in-suspend;
168 regulator-suspend-microvolt = <800000>;
169 };
170 };
171
172 vcc_1v8: LDO_REG4 {
173 regulator-name = "vcc_1v8";
174 regulator-always-on;
175 regulator-boot-on;
176 regulator-min-microvolt = <1800000>;
177 regulator-max-microvolt = <1800000>;
178 regulator-state-mem {
179 regulator-on-in-suspend;
180 regulator-suspend-microvolt = <1800000>;
181 };
182 };
183
184 vcc_dovdd: LDO_REG5 {
185 regulator-name = "vcc_dovdd";
186 regulator-always-on;
187 regulator-boot-on;
188 regulator-min-microvolt = <1800000>;
189 regulator-max-microvolt = <1800000>;
190 regulator-state-mem {
191 regulator-off-in-suspend;
192 };
193 };
194
195 vcc_dvdd: LDO_REG6 {
196 regulator-name = "vcc_dvdd";
197 regulator-min-microvolt = <1200000>;
198 regulator-max-microvolt = <1200000>;
199 regulator-state-mem {
200 regulator-off-in-suspend;
201 };
202 };
203
204 vcc_avdd: LDO_REG7 {
205 regulator-name = "vcc_avdd";
206 regulator-min-microvolt = <2800000>;
207 regulator-max-microvolt = <2800000>;
208 regulator-state-mem {
209 regulator-off-in-suspend;
210 };
211 };
212
213 vccio_sd: LDO_REG8 {
214 regulator-name = "vccio_sd";
215 regulator-always-on;
216 regulator-boot-on;
217 regulator-min-microvolt = <1800000>;
218 regulator-max-microvolt = <3300000>;
219 regulator-state-mem {
220 regulator-off-in-suspend;
221 };
222 };
223
224 vcc3v3_sd: LDO_REG9 {
225 regulator-name = "vcc3v3_sd";
226 regulator-always-on;
227 regulator-boot-on;
228 regulator-min-microvolt = <3300000>;
229 regulator-max-microvolt = <3300000>;
230 regulator-state-mem {
231 regulator-off-in-suspend;
232 };
233 };
234
235 vcc_5v0: SWITCH_REG1 {
236 regulator-name = "vcc_5v0";
237 };
238
239 vcc_3v3: SWITCH_REG2 {
240 regulator-name = "vcc_3v3";
241 regulator-always-on;
242 regulator-boot-on;
243 };
244 };
245 };
246};
247
248&i2c2 {
249 status = "okay";
250 clock-frequency = <400000>;
251
252 pcf8563: rtc@51 {
253 compatible = "nxp,pcf8563";
254 reg = <0x51>;
255 #clock-cells = <0>;
256 interrupt-parent = <&gpio0>;
257 interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>;
258 clock-output-names = "xin32k";
259 };
260};
261
262&gmac {
263 assigned-clocks = <&cru CLK_GMAC_SRC_M1>, <&cru CLK_GMAC_SRC>,
264 <&cru CLK_GMAC_TX_RX>;
265 assigned-clock-parents = <&cru CLK_GMAC_RGMII_M1>, <&cru CLK_GMAC_SRC_M1>,
266 <&cru RMII_MODE_CLK>;
267 assigned-clock-rates = <0>, <50000000>;
268 clock_in_out = "output";
269 phy-handle = <&phy>;
270 phy-mode = "rmii";
271 phy-supply = <&vcc_3v3>;
272 pinctrl-names = "default";
273 pinctrl-0 = <&rgmiim1_miim &rgmiim1_rxer &rgmiim1_bus2 &rgmiim1_mclkinout>;
274 status = "okay";
275};
276
277&mdio {
278 phy: ethernet-phy@0 {
279 compatible = "ethernet-phy-ieee802.3-c22";
280 reg = <0x0>;
281 pinctrl-names = "default";
282 pinctrl-0 = <&eth_phy_rst>;
283 reset-active-low;
284 reset-assert-us = <50000>;
285 reset-deassert-us = <10000>;
286 reset-gpios = <&gpio2 RK_PA6 GPIO_ACTIVE_LOW>;
287 };
288};
289
290&pinctrl {
291 ethernet {
292 eth_phy_rst: eth-phy-rst {
293 rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_down>;
294 };
295 };
296 bt {
297 bt_enable: bt-enable {
298 rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
299 };
300
301 bt_wake_dev: bt-wake-dev {
302 rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
303 };
304
305 bt_wake_host: bt-wake-host {
306 rockchip,pins = <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
307 };
308 };
309
310 pmic {
311 pmic_int_l: pmic-int-l {
312 rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>;
313 };
314 };
315
316 wifi {
317 wifi_enable_h: wifi-enable-h {
318 rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
319 };
320 };
321};
322
323&pmu_io_domains {
324 pmuio0-supply = <&vcc1v8_pmu>;
325 pmuio1-supply = <&vcc3v3_sys>;
326 vccio1-supply = <&vcc_1v8>;
327 vccio2-supply = <&vccio_sd>;
328 vccio3-supply = <&vcc_1v8>;
329 vccio4-supply = <&vcc_dovdd>;
330 vccio5-supply = <&vcc_1v8>;
331 vccio6-supply = <&vcc_1v8>;
332 vccio7-supply = <&vcc_dovdd>;
333 status = "okay";
334};
335
336&saradc {
337 vref-supply = <&vcc_1v8>;
338 status = "okay";
339};
340
341&sdio {
342 bus-width = <4>;
343 cap-sd-highspeed;
344 cap-sdio-irq;
345 keep-power-in-suspend;
346 max-frequency = <100000000>;
347 mmc-pwrseq = <&sdio_pwrseq>;
348 non-removable;
349 pinctrl-names = "default";
350 pinctrl-0 = <&sdmmc1_clk &sdmmc1_cmd &sdmmc1_bus4>;
351 rockchip,default-sample-phase = <90>;
352 sd-uhs-sdr104;
353 vmmc-supply = <&vcc3v3_sys>;
354 vqmmc-supply = <&vcc_1v8>;
355 status = "okay";
356};
357
358&sdmmc {
359 bus-width = <4>;
360 cap-mmc-highspeed;
361 cap-sd-highspeed;
362 card-detect-delay = <200>;
363 pinctrl-names = "default";
364 pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_bus4 &sdmmc0_det>;
365 rockchip,default-sample-phase = <90>;
366 sd-uhs-sdr12;
367 sd-uhs-sdr25;
368 sd-uhs-sdr104;
369 vqmmc-supply = <&vccio_sd>;
370 status = "okay";
371};
372
373&uart0 {
374 pinctrl-names = "default";
375 pinctrl-0 = <&uart0_xfer &uart0_ctsn &uart0_rtsn>;
376 uart-has-rtscts;
377 status = "okay";
378
379 bluetooth {
380 compatible = "realtek,rtl8723ds-bt";
381 device-wake-gpios = <&gpio1 RK_PC7 GPIO_ACTIVE_HIGH>; /* BT_WAKE */
382 enable-gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_HIGH>; /* BT_RST */
383 host-wake-gpios = <&gpio1 RK_PC5 GPIO_ACTIVE_HIGH>; /* BT_WAKE_HOST */
384 max-speed = <2000000>;
385 pinctrl-names = "default";
386 pinctrl-0 = <&bt_enable>, <&bt_wake_dev>, <&bt_wake_host>;
387 };
388};
389
390&uart2 {
391 status = "okay";
392};
393
394&uart3 {
395 pinctrl-names = "default";
396 pinctrl-0 = <&uart3m2_xfer>;
397 status = "okay";
398};
399
400&uart4 {
401 pinctrl-names = "default";
402 pinctrl-0 = <&uart4m2_xfer>;
403 status = "okay";
404};