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git01.mediatek.com / filogic / uboot / 3b829a2c0bac0f9767988942751eaac8e3ade5e0 / . / dts / upstream / src / arm / rockchip / rk3xxx.dtsi
blob: f37137f298d5f1605d0fb491624c363ea42adb8f [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2013 MundoReader S.L.
4 * Author: Heiko Stuebner <heiko@sntech.de>
5 */
6
7#include <dt-bindings/interrupt-controller/irq.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9#include <dt-bindings/soc/rockchip,boot-mode.h>
10
11/ {
12 #address-cells = <1>;
13 #size-cells = <1>;
14
15 interrupt-parent = <&gic>;
16
17 aliases {
18 ethernet0 = &emac;
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]19 gpio0 = &gpio0;
20 gpio1 = &gpio1;
21 gpio2 = &gpio2;
22 gpio3 = &gpio3;
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]23 i2c0 = &i2c0;
24 i2c1 = &i2c1;
25 i2c2 = &i2c2;
26 i2c3 = &i2c3;
27 i2c4 = &i2c4;
28 serial0 = &uart0;
29 serial1 = &uart1;
30 serial2 = &uart2;
31 serial3 = &uart3;
32 spi0 = &spi0;
33 spi1 = &spi1;
34 };
35
36 xin24m: oscillator {
37 compatible = "fixed-clock";
38 clock-frequency = <24000000>;
39 #clock-cells = <0>;
40 clock-output-names = "xin24m";
41 };
42
43 gpu: gpu@10090000 {
44 compatible = "arm,mali-400";
45 reg = <0x10090000 0x10000>;
46 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
47 clock-names = "bus", "core";
48 assigned-clocks = <&cru ACLK_GPU>;
49 assigned-clock-rates = <100000000>;
50 resets = <&cru SRST_GPU>;
51 status = "disabled";
52 };
53
54 vpu: video-codec@10104000 {
55 compatible = "rockchip,rk3066-vpu";
56 reg = <0x10104000 0x800>;
57 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
58 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
59 interrupt-names = "vepu", "vdpu";
60 clocks = <&cru ACLK_VDPU>, <&cru HCLK_VDPU>,
61 <&cru ACLK_VEPU>, <&cru HCLK_VEPU>;
62 clock-names = "aclk_vdpu", "hclk_vdpu",
63 "aclk_vepu", "hclk_vepu";
64 };
65
66 L2: cache-controller@10138000 {
67 compatible = "arm,pl310-cache";
68 reg = <0x10138000 0x1000>;
69 cache-unified;
70 cache-level = <2>;
71 };
72
73 scu@1013c000 {
74 compatible = "arm,cortex-a9-scu";
75 reg = <0x1013c000 0x100>;
76 };
77
78 global_timer: global-timer@1013c200 {
79 compatible = "arm,cortex-a9-global-timer";
80 reg = <0x1013c200 0x20>;
81 interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
82 clocks = <&cru CORE_PERI>;
83 status = "disabled";
84 /* The clock source and the sched_clock provided by the arm_global_timer
85 * on Rockchip rk3066a/rk3188 are quite unstable because their rates
86 * depend on the CPU frequency.
87 * Keep the arm_global_timer disabled in order to have the
88 * DW_APB_TIMER (rk3066a) or ROCKCHIP_TIMER (rk3188) selected by default.
89 */
90 };
91
92 local_timer: local-timer@1013c600 {
93 compatible = "arm,cortex-a9-twd-timer";
94 reg = <0x1013c600 0x20>;
95 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
96 clocks = <&cru CORE_PERI>;
97 };
98
99 gic: interrupt-controller@1013d000 {
100 compatible = "arm,cortex-a9-gic";
101 interrupt-controller;
102 #interrupt-cells = <3>;
103 reg = <0x1013d000 0x1000>,
104 <0x1013c100 0x0100>;
105 };
106
107 uart0: serial@10124000 {
108 compatible = "snps,dw-apb-uart";
109 reg = <0x10124000 0x400>;
110 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
111 reg-shift = <2>;
112 reg-io-width = <1>;
113 clock-names = "baudclk", "apb_pclk";
114 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
115 status = "disabled";
116 };
117
118 uart1: serial@10126000 {
119 compatible = "snps,dw-apb-uart";
120 reg = <0x10126000 0x400>;
121 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
122 reg-shift = <2>;
123 reg-io-width = <1>;
124 clock-names = "baudclk", "apb_pclk";
125 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
126 status = "disabled";
127 };
128
129 qos_gpu: qos@1012d000 {
130 compatible = "rockchip,rk3066-qos", "syscon";
131 reg = <0x1012d000 0x20>;
132 };
133
134 qos_vpu: qos@1012e000 {
135 compatible = "rockchip,rk3066-qos", "syscon";
136 reg = <0x1012e000 0x20>;
137 };
138
139 qos_lcdc0: qos@1012f000 {
140 compatible = "rockchip,rk3066-qos", "syscon";
141 reg = <0x1012f000 0x20>;
142 };
143
144 qos_cif0: qos@1012f080 {
145 compatible = "rockchip,rk3066-qos", "syscon";
146 reg = <0x1012f080 0x20>;
147 };
148
149 qos_ipp: qos@1012f100 {
150 compatible = "rockchip,rk3066-qos", "syscon";
151 reg = <0x1012f100 0x20>;
152 };
153
154 qos_lcdc1: qos@1012f180 {
155 compatible = "rockchip,rk3066-qos", "syscon";
156 reg = <0x1012f180 0x20>;
157 };
158
159 qos_cif1: qos@1012f200 {
160 compatible = "rockchip,rk3066-qos", "syscon";
161 reg = <0x1012f200 0x20>;
162 };
163
164 qos_rga: qos@1012f280 {
165 compatible = "rockchip,rk3066-qos", "syscon";
166 reg = <0x1012f280 0x20>;
167 };
168
169 usb_otg: usb@10180000 {
170 compatible = "rockchip,rk3066-usb", "snps,dwc2";
171 reg = <0x10180000 0x40000>;
172 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
173 clocks = <&cru HCLK_OTG0>;
174 clock-names = "otg";
175 dr_mode = "otg";
176 g-np-tx-fifo-size = <16>;
177 g-rx-fifo-size = <275>;
178 g-tx-fifo-size = <256 128 128 64 64 32>;
179 phys = <&usbphy0>;
180 phy-names = "usb2-phy";
181 status = "disabled";
182 };
183
184 usb_host: usb@101c0000 {
185 compatible = "snps,dwc2";
186 reg = <0x101c0000 0x40000>;
187 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
188 clocks = <&cru HCLK_OTG1>;
189 clock-names = "otg";
190 dr_mode = "host";
191 phys = <&usbphy1>;
192 phy-names = "usb2-phy";
193 status = "disabled";
194 };
195
196 emac: ethernet@10204000 {
197 compatible = "snps,arc-emac";
198 reg = <0x10204000 0x3c>;
199 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
200
201 rockchip,grf = <&grf>;
202
203 clocks = <&cru HCLK_EMAC>, <&cru SCLK_MAC>;
204 clock-names = "hclk", "macref";
205 max-speed = <100>;
206 phy-mode = "rmii";
207
208 status = "disabled";
209 };
210
211 mmc0: mmc@10214000 {
212 compatible = "rockchip,rk2928-dw-mshc";
213 reg = <0x10214000 0x1000>;
214 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
215 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
216 clock-names = "biu", "ciu";
217 dmas = <&dmac2 1>;
218 dma-names = "rx-tx";
219 fifo-depth = <256>;
220 resets = <&cru SRST_SDMMC>;
221 reset-names = "reset";
222 status = "disabled";
223 };
224
225 mmc1: mmc@10218000 {
226 compatible = "rockchip,rk2928-dw-mshc";
227 reg = <0x10218000 0x1000>;
228 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
229 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>;
230 clock-names = "biu", "ciu";
231 dmas = <&dmac2 3>;
232 dma-names = "rx-tx";
233 fifo-depth = <256>;
234 resets = <&cru SRST_SDIO>;
235 reset-names = "reset";
236 status = "disabled";
237 };
238
239 emmc: mmc@1021c000 {
240 compatible = "rockchip,rk2928-dw-mshc";
241 reg = <0x1021c000 0x1000>;
242 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
243 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
244 clock-names = "biu", "ciu";
245 dmas = <&dmac2 4>;
246 dma-names = "rx-tx";
247 fifo-depth = <256>;
248 resets = <&cru SRST_EMMC>;
249 reset-names = "reset";
250 status = "disabled";
251 };
252
253 nfc: nand-controller@10500000 {
254 compatible = "rockchip,rk2928-nfc";
255 reg = <0x10500000 0x4000>;
256 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
257 clocks = <&cru HCLK_NANDC0>;
258 clock-names = "ahb";
259 status = "disabled";
260 };
261
262 pmu: pmu@20004000 {
263 compatible = "rockchip,rk3066-pmu", "syscon", "simple-mfd";
264 reg = <0x20004000 0x100>;
265
266 reboot-mode {
267 compatible = "syscon-reboot-mode";
268 offset = <0x40>;
269 mode-normal = <BOOT_NORMAL>;
270 mode-recovery = <BOOT_RECOVERY>;
271 mode-bootloader = <BOOT_FASTBOOT>;
272 mode-loader = <BOOT_BL_DOWNLOAD>;
273 };
274 };
275
276 grf: grf@20008000 {
277 compatible = "syscon", "simple-mfd";
278 reg = <0x20008000 0x200>;
279 };
280
281 dmac1_s: dma-controller@20018000 {
282 compatible = "arm,pl330", "arm,primecell";
283 reg = <0x20018000 0x4000>;
284 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
285 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
286 #dma-cells = <1>;
287 arm,pl330-broken-no-flushp;
288 arm,pl330-periph-burst;
289 clocks = <&cru ACLK_DMA1>;
290 clock-names = "apb_pclk";
291 };
292
293 dmac1_ns: dma-controller@2001c000 {
294 compatible = "arm,pl330", "arm,primecell";
295 reg = <0x2001c000 0x4000>;
296 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
297 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
298 #dma-cells = <1>;
299 arm,pl330-broken-no-flushp;
300 arm,pl330-periph-burst;
301 clocks = <&cru ACLK_DMA1>;
302 clock-names = "apb_pclk";
303 status = "disabled";
304 };
305
306 i2c0: i2c@2002d000 {
307 compatible = "rockchip,rk3066-i2c";
308 reg = <0x2002d000 0x1000>;
309 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
310 #address-cells = <1>;
311 #size-cells = <0>;
312
313 rockchip,grf = <&grf>;
314
315 clock-names = "i2c";
316 clocks = <&cru PCLK_I2C0>;
317
318 status = "disabled";
319 };
320
321 i2c1: i2c@2002f000 {
322 compatible = "rockchip,rk3066-i2c";
323 reg = <0x2002f000 0x1000>;
324 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
325 #address-cells = <1>;
326 #size-cells = <0>;
327
328 rockchip,grf = <&grf>;
329
330 clocks = <&cru PCLK_I2C1>;
331 clock-names = "i2c";
332
333 status = "disabled";
334 };
335
336 pwm0: pwm@20030000 {
337 compatible = "rockchip,rk2928-pwm";
338 reg = <0x20030000 0x10>;
339 #pwm-cells = <2>;
340 clocks = <&cru PCLK_PWM01>;
341 status = "disabled";
342 };
343
344 pwm1: pwm@20030010 {
345 compatible = "rockchip,rk2928-pwm";
346 reg = <0x20030010 0x10>;
347 #pwm-cells = <2>;
348 clocks = <&cru PCLK_PWM01>;
349 status = "disabled";
350 };
351
352 wdt: watchdog@2004c000 {
353 compatible = "snps,dw-wdt";
354 reg = <0x2004c000 0x100>;
355 clocks = <&cru PCLK_WDT>;
356 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
357 status = "disabled";
358 };
359
360 pwm2: pwm@20050020 {
361 compatible = "rockchip,rk2928-pwm";
362 reg = <0x20050020 0x10>;
363 #pwm-cells = <2>;
364 clocks = <&cru PCLK_PWM23>;
365 status = "disabled";
366 };
367
368 pwm3: pwm@20050030 {
369 compatible = "rockchip,rk2928-pwm";
370 reg = <0x20050030 0x10>;
371 #pwm-cells = <2>;
372 clocks = <&cru PCLK_PWM23>;
373 status = "disabled";
374 };
375
376 i2c2: i2c@20056000 {
377 compatible = "rockchip,rk3066-i2c";
378 reg = <0x20056000 0x1000>;
379 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
380 #address-cells = <1>;
381 #size-cells = <0>;
382
383 rockchip,grf = <&grf>;
384
385 clocks = <&cru PCLK_I2C2>;
386 clock-names = "i2c";
387
388 status = "disabled";
389 };
390
391 i2c3: i2c@2005a000 {
392 compatible = "rockchip,rk3066-i2c";
393 reg = <0x2005a000 0x1000>;
394 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
395 #address-cells = <1>;
396 #size-cells = <0>;
397
398 rockchip,grf = <&grf>;
399
400 clocks = <&cru PCLK_I2C3>;
401 clock-names = "i2c";
402
403 status = "disabled";
404 };
405
406 i2c4: i2c@2005e000 {
407 compatible = "rockchip,rk3066-i2c";
408 reg = <0x2005e000 0x1000>;
409 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
410 #address-cells = <1>;
411 #size-cells = <0>;
412
413 rockchip,grf = <&grf>;
414
415 clocks = <&cru PCLK_I2C4>;
416 clock-names = "i2c";
417
418 status = "disabled";
419 };
420
421 uart2: serial@20064000 {
422 compatible = "snps,dw-apb-uart";
423 reg = <0x20064000 0x400>;
424 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
425 reg-shift = <2>;
426 reg-io-width = <1>;
427 clock-names = "baudclk", "apb_pclk";
428 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
429 status = "disabled";
430 };
431
432 uart3: serial@20068000 {
433 compatible = "snps,dw-apb-uart";
434 reg = <0x20068000 0x400>;
435 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
436 reg-shift = <2>;
437 reg-io-width = <1>;
438 clock-names = "baudclk", "apb_pclk";
439 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
440 status = "disabled";
441 };
442
443 saradc: saradc@2006c000 {
444 compatible = "rockchip,saradc";
445 reg = <0x2006c000 0x100>;
446 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
447 #io-channel-cells = <1>;
448 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
449 clock-names = "saradc", "apb_pclk";
450 resets = <&cru SRST_SARADC>;
451 reset-names = "saradc-apb";
452 status = "disabled";
453 };
454
455 spi0: spi@20070000 {
456 compatible = "rockchip,rk3066-spi";
457 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
458 clock-names = "spiclk", "apb_pclk";
459 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
460 reg = <0x20070000 0x1000>;
461 #address-cells = <1>;
462 #size-cells = <0>;
463 dmas = <&dmac2 10>, <&dmac2 11>;
464 dma-names = "tx", "rx";
465 status = "disabled";
466 };
467
468 spi1: spi@20074000 {
469 compatible = "rockchip,rk3066-spi";
470 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
471 clock-names = "spiclk", "apb_pclk";
472 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
473 reg = <0x20074000 0x1000>;
474 #address-cells = <1>;
475 #size-cells = <0>;
476 dmas = <&dmac2 12>, <&dmac2 13>;
477 dma-names = "tx", "rx";
478 status = "disabled";
479 };
480
481 dmac2: dma-controller@20078000 {
482 compatible = "arm,pl330", "arm,primecell";
483 reg = <0x20078000 0x4000>;
484 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
485 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
486 #dma-cells = <1>;
487 arm,pl330-broken-no-flushp;
488 arm,pl330-periph-burst;
489 clocks = <&cru ACLK_DMA2>;
490 clock-names = "apb_pclk";
491 };
492};