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git01.mediatek.com / filogic / uboot / 3b829a2c0bac0f9767988942751eaac8e3ade5e0 / . / dts / upstream / src / arm / rockchip / rk3288-veyron-jerry.dts
blob: 6894763979f035bc827404a04ca0a089a3e92a80 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Google Veyron Jerry Rev 3+ board device tree source
4 *
5 * Copyright 2015 Google, Inc
6 */
7
8/dts-v1/;
9#include "rk3288-veyron-chromebook.dtsi"
10#include "../cros-ec-sbs.dtsi"
11
12/ {
13 model = "Google Jerry";
14 compatible = "google,veyron-jerry-rev15", "google,veyron-jerry-rev14",
15 "google,veyron-jerry-rev13", "google,veyron-jerry-rev12",
16 "google,veyron-jerry-rev11", "google,veyron-jerry-rev10",
17 "google,veyron-jerry-rev7", "google,veyron-jerry-rev6",
18 "google,veyron-jerry-rev5", "google,veyron-jerry-rev4",
19 "google,veyron-jerry-rev3", "google,veyron-jerry",
20 "google,veyron", "rockchip,rk3288";
21};
22
23&rk808 {
24 pinctrl-names = "default";
25 pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>;
26 dvs-gpios = <&gpio7 RK_PB4 GPIO_ACTIVE_HIGH>,
27 <&gpio7 RK_PB7 GPIO_ACTIVE_HIGH>;
28
29 regulators {
30 mic_vcc: LDO_REG2 {
31 regulator-name = "mic_vcc";
32 regulator-always-on;
33 regulator-boot-on;
34 regulator-min-microvolt = <1800000>;
35 regulator-max-microvolt = <1800000>;
36 regulator-state-mem {
37 regulator-off-in-suspend;
38 };
39 };
40 };
41};
42
43&sdio0 {
44 #address-cells = <1>;
45 #size-cells = <0>;
46
47 mwifiex: wifi@1 {
48 compatible = "marvell,sd8897";
49 reg = <1>;
50
51 marvell,caldata-txpwrlimit-2g = /bits/ 8 <
520x01 0x00 0x06 0x00 0x08 0x02 0x89 0x01
530x24 0x00 0x67 0x09 0x14 0x01 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c
540x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c
550x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 0x24 0x00 0x67 0x09 0x14 0x02 0x00 0x0f
560x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09
570x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01
580x24 0x00 0x67 0x09 0x14 0x03 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c
590x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c
600x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 0x24 0x00 0x67 0x09 0x14 0x04 0x00 0x0f
610x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09
620x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01
630x24 0x00 0x67 0x09 0x14 0x05 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c
640x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c
650x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 0x24 0x00 0x67 0x09 0x14 0x06 0x00 0x0f
660x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09
670x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01
680x24 0x00 0x67 0x09 0x14 0x07 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c
690x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c
700x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 0x24 0x00 0x67 0x09 0x14 0x08 0x00 0x0f
710x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09
720x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01
730x24 0x00 0x67 0x09 0x14 0x09 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c
740x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c
750x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 0x24 0x00 0x67 0x09 0x14 0x0a 0x00 0x0f
760x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09
770x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01
780x24 0x00 0x67 0x09 0x14 0x0b 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c
790x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c
800x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01 0x24 0x00 0x67 0x09 0x14 0x0c 0x00 0x0f
810x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c 0x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09
820x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x89 0x01
830x24 0x00 0x67 0x09 0x14 0x0d 0x00 0x0f 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0c
840x05 0x0c 0x06 0x0c 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0c 0x0b 0x0c 0x0c 0x0c
850x0d 0x09 0x0e 0x09 0x0f 0x09>;
86
87 marvell,caldata-txpwrlimit-5g-sub0 = /bits/ 8 <
880x01 0x00 0x06 0x00 0xf0 0x01 0x89 0x01
890x3a 0x00 0x88 0x13 0x14 0x24 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a
900x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09
910x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05
920x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00
930x88 0x13 0x14 0x28 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a
940x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09
950x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05
960x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13
970x14 0x2c 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09
980x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09
990x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05
1000x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x30
1010x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09
1020x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05
1030x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05
1040x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x34 0x01 0x0c
1050x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09
1060x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05
1070x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05
1080x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x38 0x01 0x0c 0x02 0x0c
1090x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a
1100x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05
1110x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05
1120x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x3c 0x01 0x0c 0x02 0x0c 0x03 0x0c
1130x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a
1140x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05
1150x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05
1160x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x40 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a
1170x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a
1180x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05
1190x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05>;
120
121 marvell,caldata-txpwrlimit-5g-sub1 = /bits/ 8 <
1220x01 0x00 0x06 0x00 0xaa 0x02 0x89 0x01
1230x3a 0x00 0x88 0x13 0x14 0x64 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a
1240x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09
1250x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05
1260x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00
1270x88 0x13 0x14 0x68 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a
1280x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09
1290x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05
1300x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13
1310x14 0x6c 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09
1320x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09
1330x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05
1340x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x70
1350x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09
1360x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05
1370x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05
1380x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x74 0x01 0x0c
1390x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09
1400x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05
1410x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05
1420x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x78 0x01 0x0c 0x02 0x0c
1430x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a
1440x0b 0x0a 0x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05
1450x13 0x05 0x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05
1460x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x7c 0x01 0x0c 0x02 0x0c 0x03 0x0c
1470x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a
1480x0c 0x0a 0x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05
1490x14 0x05 0x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05
1500x89 0x01 0x3a 0x00 0x88 0x13 0x14 0x80 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a
1510x05 0x0a 0x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a
1520x0d 0x09 0x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05
1530x15 0x05 0x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01
1540x3a 0x00 0x88 0x13 0x14 0x84 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a
1550x06 0x0a 0x07 0x09 0x08 0x09 0x09 0x09 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x09
1560x0e 0x09 0x0f 0x09 0x10 0x05 0x11 0x05 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05
1570x16 0x05 0x17 0x05 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00
1580x88 0x13 0x14 0x88 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a
1590x07 0x08 0x08 0x08 0x09 0x08 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x08 0x0e 0x08
1600x0f 0x08 0x10 0x04 0x11 0x04 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x04
1610x17 0x04 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13
1620x14 0x8c 0x01 0x0c 0x02 0x0c 0x03 0x0c 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x08
1630x08 0x08 0x09 0x08 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x08 0x0e 0x08 0x0f 0x08
1640x10 0x04 0x11 0x04 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x04 0x17 0x04
1650x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05>;
166
167 marvell,caldata-txpwrlimit-5g-sub2 = /bits/ 8 <
1680x01 0x00 0x06 0x00 0x36 0x01 0x89 0x01
1690x3a 0x00 0x88 0x13 0x14 0x95 0x01 0x0b 0x02 0x0b 0x03 0x0b 0x04 0x0a 0x05 0x0a
1700x06 0x0a 0x07 0x08 0x08 0x08 0x09 0x08 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x08
1710x0e 0x08 0x0f 0x08 0x10 0x04 0x11 0x04 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05
1720x16 0x04 0x17 0x04 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00
1730x88 0x13 0x14 0x99 0x01 0x0b 0x02 0x0b 0x03 0x0b 0x04 0x0a 0x05 0x0a 0x06 0x0a
1740x07 0x08 0x08 0x08 0x09 0x08 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x08 0x0e 0x08
1750x0f 0x08 0x10 0x04 0x11 0x04 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x04
1760x17 0x04 0x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13
1770x14 0x9d 0x01 0x0b 0x02 0x0b 0x03 0x0b 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x08
1780x08 0x08 0x09 0x08 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x08 0x0e 0x08 0x0f 0x08
1790x10 0x04 0x11 0x04 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x04 0x17 0x04
1800x18 0x05 0x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0xa1
1810x01 0x0b 0x02 0x0b 0x03 0x0b 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x08 0x08 0x08
1820x09 0x08 0x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x08 0x0e 0x08 0x0f 0x08 0x10 0x04
1830x11 0x04 0x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x04 0x17 0x04 0x18 0x05
1840x19 0x05 0x1a 0x05 0x1b 0x05 0x89 0x01 0x3a 0x00 0x88 0x13 0x14 0xa5 0x01 0x0b
1850x02 0x0b 0x03 0x0b 0x04 0x0a 0x05 0x0a 0x06 0x0a 0x07 0x08 0x08 0x08 0x09 0x08
1860x0a 0x0a 0x0b 0x0a 0x0c 0x0a 0x0d 0x08 0x0e 0x08 0x0f 0x08 0x10 0x04 0x11 0x04
1870x12 0x05 0x13 0x05 0x14 0x05 0x15 0x05 0x16 0x04 0x17 0x04 0x18 0x05 0x19 0x05
1880x1a 0x05 0x1b 0x05>;
189 };
190};
191
192&sdmmc {
193 disable-wp;
194 pinctrl-names = "default";
195 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_pin
196 &sdmmc_bus4>;
197};
198
199&vcc_5v {
200 enable-active-high;
201 gpio = <&gpio7 RK_PC5 GPIO_ACTIVE_HIGH>;
202 pinctrl-names = "default";
203 pinctrl-0 = <&drv_5v>;
204};
205
206&vcc50_hdmi {
207 enable-active-high;
208 gpio = <&gpio5 RK_PC3 GPIO_ACTIVE_HIGH>;
209 pinctrl-names = "default";
210 pinctrl-0 = <&vcc50_hdmi_en>;
211};
212
213&gpio0 {
214 gpio-line-names = "PMIC_SLEEP_AP",
215 "DDRIO_PWROFF",
216 "DDRIO_RETEN",
217 "TS3A227E_INT_L",
218 "PMIC_INT_L",
219 "PWR_KEY_L",
220 "AP_LID_INT_L",
221 "EC_IN_RW",
222
223 "AC_PRESENT_AP",
224 /*
225 * RECOVERY_SW_L is Chrome OS ABI. Schematics call
226 * it REC_MODE_L.
227 */
228 "RECOVERY_SW_L",
229 "OTP_OUT",
230 "HOST1_PWR_EN",
231 "USBOTG_PWREN_H",
232 "AP_WARM_RESET_H",
233 "nFAULT2",
234 "I2C0_SDA_PMIC",
235
236 "I2C0_SCL_PMIC",
237 "SUSPEND_L",
238 "USB_INT";
239};
240
241&gpio2 {
242 gpio-line-names = "CONFIG0",
243 "CONFIG1",
244 "CONFIG2",
245 "",
246 "",
247 "",
248 "",
249 "CONFIG3",
250
251 "",
252 "EMMC_RST_L",
253 "",
254 "",
255 "BL_PWR_EN",
256 "AVDD_1V8_DISP_EN";
257};
258
259&gpio3 {
260 gpio-line-names = "FLASH0_D0",
261 "FLASH0_D1",
262 "FLASH0_D2",
263 "FLASH0_D3",
264 "FLASH0_D4",
265 "FLASH0_D5",
266 "FLASH0_D6",
267 "FLASH0_D7",
268
269 "",
270 "",
271 "",
272 "",
273 "",
274 "",
275 "",
276 "",
277
278 "FLASH0_CS2/EMMC_CMD",
279 "",
280 "FLASH0_DQS/EMMC_CLKO";
281};
282
283&gpio4 {
284 gpio-line-names = "",
285 "",
286 "",
287 "",
288 "",
289 "",
290 "",
291 "",
292
293 "",
294 "",
295 "",
296 "",
297 "",
298 "",
299 "",
300 "",
301
302 "UART0_RXD",
303 "UART0_TXD",
304 "UART0_CTS",
305 "UART0_RTS",
306 "SDIO0_D0",
307 "SDIO0_D1",
308 "SDIO0_D2",
309 "SDIO0_D3",
310
311 "SDIO0_CMD",
312 "SDIO0_CLK",
313 "BT_DEV_WAKE",
314 "",
315 "WIFI_ENABLE_H",
316 "BT_ENABLE_L",
317 "WIFI_HOST_WAKE",
318 "BT_HOST_WAKE";
319};
320
321&gpio5 {
322 gpio-line-names = "",
323 "",
324 "",
325 "",
326 "",
327 "",
328 "",
329 "",
330
331 "",
332 "",
333 "",
334 "",
335 "SPI0_CLK",
336 "SPI0_CS0",
337 "SPI0_TXD",
338 "SPI0_RXD",
339
340 "",
341 "",
342 "",
343 "VCC50_HDMI_EN";
344};
345
346&gpio6 {
347 gpio-line-names = "I2S0_SCLK",
348 "I2S0_LRCK_RX",
349 "I2S0_LRCK_TX",
350 "I2S0_SDI",
351 "I2S0_SDO0",
352 "HP_DET_H",
353 "",
354 "INT_CODEC",
355
356 "I2S0_CLK",
357 "I2C2_SDA",
358 "I2C2_SCL",
359 "MICDET",
360 "",
361 "",
362 "",
363 "",
364
365 "SDMMC_D0",
366 "SDMMC_D1",
367 "SDMMC_D2",
368 "SDMMC_D3",
369 "SDMMC_CLK",
370 "SDMMC_CMD";
371};
372
373&gpio7 {
374 gpio-line-names = "LCDC_BL",
375 "PWM_LOG",
376 "BL_EN",
377 "TRACKPAD_INT",
378 "TPM_INT_H",
379 "SDMMC_DET_L",
380 /*
381 * AP_FLASH_WP_L is Chrome OS ABI. Schematics call
382 * it FW_WP_AP.
383 */
384 "AP_FLASH_WP_L",
385 "EC_INT",
386
387 "CPU_NMI",
388 "DVSOK",
389 "",
390 "EDP_HPD",
391 "DVS1",
392 "nFAULT1",
393 "LCD_EN",
394 "DVS2",
395
396 "VCC5V_GOOD_H",
397 "I2C4_SDA_TP",
398 "I2C4_SCL_TP",
399 "I2C5_SDA_HDMI",
400 "I2C5_SCL_HDMI",
401 "5V_DRV",
402 "UART2_RXD",
403 "UART2_TXD";
404};
405
406&gpio8 {
407 gpio-line-names = "RAM_ID0",
408 "RAM_ID1",
409 "RAM_ID2",
410 "RAM_ID3",
411 "I2C1_SDA_TPM",
412 "I2C1_SCL_TPM",
413 "SPI2_CLK",
414 "SPI2_CS0",
415
416 "SPI2_RXD",
417 "SPI2_TXD";
418};
419
420&pinctrl {
421 pinctrl-names = "default", "sleep";
422 pinctrl-0 = <
423 /* Common for sleep and wake, but no owners */
424 &ddr0_retention
425 &ddrio_pwroff
426 &global_pwroff
427
428 /* Wake only */
429 &suspend_l_wake
430 &bt_dev_wake_awake
431 >;
432 pinctrl-1 = <
433 /* Common for sleep and wake, but no owners */
434 &ddr0_retention
435 &ddrio_pwroff
436 &global_pwroff
437
438 /* Sleep only */
439 &suspend_l_sleep
440 &bt_dev_wake_sleep
441 >;
442
443 buck-5v {
444 drv_5v: drv-5v {
445 rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
446 };
447 };
448
449 hdmi {
450 vcc50_hdmi_en: vcc50-hdmi-en {
451 rockchip,pins = <5 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
452 };
453 };
454
455 pmic {
456 dvs_1: dvs-1 {
457 rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;
458 };
459
460 dvs_2: dvs-2 {
461 rockchip,pins = <7 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>;
462 };
463 };
464};
465
466&i2c4 {
467 status = "okay";
468
469 /*
470 * Trackpad pin control is shared between Elan and Synaptics devices
471 * so we have to pull it up to the bus level.
472 */
473 pinctrl-names = "default";
474 pinctrl-0 = <&i2c4_xfer &trackpad_int>;
475
476 trackpad@15 {
477 /*
478 * Remove the inherited pinctrl settings to avoid clashing
479 * with bus-wide ones.
480 */
481 /delete-property/pinctrl-names;
482 /delete-property/pinctrl-0;
483 };
484
485 trackpad@2c {
486 compatible = "hid-over-i2c";
487 interrupt-parent = <&gpio7>;
488 interrupts = <RK_PA3 IRQ_TYPE_EDGE_FALLING>;
489 reg = <0x2c>;
490 hid-descr-addr = <0x0020>;
491 vcc-supply = <&vcc33_io>;
492 wakeup-source;
493 };
494};