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git01.mediatek.com / filogic / uboot / 3b79050b0f8dda536773a5f4c4105dbf5379b6d6 / . / include / asm-m68k / m5282.h
blob: 7473bb9be65e4c31bcc15812d93112869d8caecf [file] [log] [blame]
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]1/*
2 * mcf5282.h -- Definitions for Motorola Coldfire 5282
3 *
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23/****************************************************************************/
24#ifndef m5282_h
25#define m5282_h
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]26
27/*********************************************************************
28* PLL Clock Module
29*********************************************************************/
30/* Bit definitions and macros for PLL_SYNCR */
31#define PLL_SYNCR_LOLRE (0x8000)
32#define PLL_SYNCR_MFD2 (0x4000)
33#define PLL_SYNCR_MFD1 (0x2000)
34#define PLL_SYNCR_MFD0 (0x1000)
35#define PLL_SYNCR_LOCRE (0x0800)
36#define PLL_SYNCR_RFC2 (0x0400)
37#define PLL_SYNCR_RFC1 (0x0200)
38#define PLL_SYNCR_RFC0 (0x0100)
39#define PLL_SYNCR_LOCEN (0x0080)
40#define PLL_SYNCR_DISCLK (0x0040)
41#define PLL_SYNCR_FWKUP (0x0020)
42#define PLL_SYNCR_STPMD1 (0x0008)
43#define PLL_SYNCR_STPMD0 (0x0004)
44
45/* Bit definitions and macros for PLL_SYNSR */
46#define PLL_SYNSR_MODE (0x0080)
47#define PLL_SYNSR_PLLSEL (0x0040)
48#define PLL_SYNSR_PLLREF (0x0020)
49#define PLL_SYNSR_LOCKS (0x0010)
50#define PLL_SYNSR_LOCK (0x0008)
51#define PLL_SYNSR_LOCS (0x0004)
52
53/*********************************************************************
54* Interrupt Controller (INTC)
55*********************************************************************/
56#define INT0_LO_RSVD0 (0)
57#define INT0_LO_EPORT1 (1)
58#define INT0_LO_EPORT2 (2)
59#define INT0_LO_EPORT3 (3)
60#define INT0_LO_EPORT4 (4)
61#define INT0_LO_EPORT5 (5)
62#define INT0_LO_EPORT6 (6)
63#define INT0_LO_EPORT7 (7)
64#define INT0_LO_SCM_SWT1 (8)
65#define INT0_LO_DMA_00 (9)
66#define INT0_LO_DMA_01 (10)
67#define INT0_LO_DMA_02 (11)
68#define INT0_LO_DMA_03 (12)
69#define INT0_LO_UART0 (13)
70#define INT0_LO_UART1 (14)
71#define INT0_LO_UART2 (15)
72#define INT0_LO_RSVD1 (16)
73#define INT0_LO_I2C (17)
74#define INT0_LO_QSPI (18)
75#define INT0_LO_DTMR0 (19)
76#define INT0_LO_DTMR1 (20)
77#define INT0_LO_DTMR2 (21)
78#define INT0_LO_DTMR3 (22)
79#define INT0_LO_FEC_TXF (23)
80#define INT0_LO_FEC_TXB (24)
81#define INT0_LO_FEC_UN (25)
82#define INT0_LO_FEC_RL (26)
83#define INT0_LO_FEC_RXF (27)
84#define INT0_LO_FEC_RXB (28)
85#define INT0_LO_FEC_MII (29)
86#define INT0_LO_FEC_LC (30)
87#define INT0_LO_FEC_HBERR (31)
88#define INT0_HI_FEC_GRA (32)
89#define INT0_HI_FEC_EBERR (33)
90#define INT0_HI_FEC_BABT (34)
91#define INT0_HI_FEC_BABR (35)
92#define INT0_HI_PMM_LVDF (36)
93#define INT0_HI_QADC_CF1 (37)
94#define INT0_HI_QADC_CF2 (38)
95#define INT0_HI_QADC_PF1 (39)
96#define INT0_HI_QADC_PF2 (40)
97#define INT0_HI_GPTA_TOF (41)
98#define INT0_HI_GPTA_PAIF (42)
99#define INT0_HI_GPTA_PAOVF (43)
100#define INT0_HI_GPTA_C0F (44)
101#define INT0_HI_GPTA_C1F (45)
102#define INT0_HI_GPTA_C2F (46)
103#define INT0_HI_GPTA_C3F (47)
104#define INT0_HI_GPTB_TOF (48)
105#define INT0_HI_GPTB_PAIF (49)
106#define INT0_HI_GPTB_PAOVF (50)
107#define INT0_HI_GPTB_C0F (51)
108#define INT0_HI_GPTB_C1F (52)
109#define INT0_HI_GPTB_C2F (53)
110#define INT0_HI_GPTB_C3F (54)
111#define INT0_HI_PIT0 (55)
112#define INT0_HI_PIT1 (56)
113#define INT0_HI_PIT2 (57)
114#define INT0_HI_PIT3 (58)
115#define INT0_HI_CFM_CBEIF (59)
116#define INT0_HI_CFM_CCIF (60)
117#define INT0_HI_CFM_PVIF (61)
118#define INT0_HI_CFM_AEIF (62)
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]119
120/*
121 * Size of internal RAM
122 */
123
124#define INT_RAM_SIZE 65536
125
Heiko Schocherac1956e2006-04-20 08:42:42 +0200[diff] [blame]126/* General Purpose I/O Module GPIO */
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]127
Heiko Schocherac1956e2006-04-20 08:42:42 +0200[diff] [blame]128#define MCFGPIO_PORTA (*(vu_char *) (CFG_MBAR+0x100000))
129#define MCFGPIO_PORTB (*(vu_char *) (CFG_MBAR+0x100001))
130#define MCFGPIO_PORTC (*(vu_char *) (CFG_MBAR+0x100002))
131#define MCFGPIO_PORTD (*(vu_char *) (CFG_MBAR+0x100003))
132#define MCFGPIO_PORTE (*(vu_char *) (CFG_MBAR+0x100004))
133#define MCFGPIO_PORTF (*(vu_char *) (CFG_MBAR+0x100005))
134#define MCFGPIO_PORTG (*(vu_char *) (CFG_MBAR+0x100006))
135#define MCFGPIO_PORTH (*(vu_char *) (CFG_MBAR+0x100007))
136#define MCFGPIO_PORTJ (*(vu_char *) (CFG_MBAR+0x100008))
137#define MCFGPIO_PORTDD (*(vu_char *) (CFG_MBAR+0x100009))
138#define MCFGPIO_PORTEH (*(vu_char *) (CFG_MBAR+0x10000A))
139#define MCFGPIO_PORTEL (*(vu_char *) (CFG_MBAR+0x10000B))
140#define MCFGPIO_PORTAS (*(vu_char *) (CFG_MBAR+0x10000C))
141#define MCFGPIO_PORTQS (*(vu_char *) (CFG_MBAR+0x10000D))
142#define MCFGPIO_PORTSD (*(vu_char *) (CFG_MBAR+0x10000E))
143#define MCFGPIO_PORTTC (*(vu_char *) (CFG_MBAR+0x10000F))
144#define MCFGPIO_PORTTD (*(vu_char *) (CFG_MBAR+0x100010))
145#define MCFGPIO_PORTUA (*(vu_char *) (CFG_MBAR+0x100011))
146
147#define MCFGPIO_DDRA (*(vu_char *) (CFG_MBAR+0x100014))
148#define MCFGPIO_DDRB (*(vu_char *) (CFG_MBAR+0x100015))
149#define MCFGPIO_DDRC (*(vu_char *) (CFG_MBAR+0x100016))
150#define MCFGPIO_DDRD (*(vu_char *) (CFG_MBAR+0x100017))
151#define MCFGPIO_DDRE (*(vu_char *) (CFG_MBAR+0x100018))
152#define MCFGPIO_DDRF (*(vu_char *) (CFG_MBAR+0x100019))
153#define MCFGPIO_DDRG (*(vu_char *) (CFG_MBAR+0x10001A))
154#define MCFGPIO_DDRH (*(vu_char *) (CFG_MBAR+0x10001B))
155#define MCFGPIO_DDRJ (*(vu_char *) (CFG_MBAR+0x10001C))
156#define MCFGPIO_DDRDD (*(vu_char *) (CFG_MBAR+0x10001D))
157#define MCFGPIO_DDREH (*(vu_char *) (CFG_MBAR+0x10001E))
158#define MCFGPIO_DDREL (*(vu_char *) (CFG_MBAR+0x10001F))
159#define MCFGPIO_DDRAS (*(vu_char *) (CFG_MBAR+0x100020))
160#define MCFGPIO_DDRQS (*(vu_char *) (CFG_MBAR+0x100021))
161#define MCFGPIO_DDRSD (*(vu_char *) (CFG_MBAR+0x100022))
162#define MCFGPIO_DDRTC (*(vu_char *) (CFG_MBAR+0x100023))
163#define MCFGPIO_DDRTD (*(vu_char *) (CFG_MBAR+0x100024))
164#define MCFGPIO_DDRUA (*(vu_char *) (CFG_MBAR+0x100025))
165
166#define MCFGPIO_PORTAP (*(vu_char *) (CFG_MBAR+0x100028))
167#define MCFGPIO_PORTBP (*(vu_char *) (CFG_MBAR+0x100029))
168#define MCFGPIO_PORTCP (*(vu_char *) (CFG_MBAR+0x10002A))
169#define MCFGPIO_PORTDP (*(vu_char *) (CFG_MBAR+0x10002B))
170#define MCFGPIO_PORTEP (*(vu_char *) (CFG_MBAR+0x10002C))
171#define MCFGPIO_PORTFP (*(vu_char *) (CFG_MBAR+0x10002D))
172#define MCFGPIO_PORTGP (*(vu_char *) (CFG_MBAR+0x10002E))
173#define MCFGPIO_PORTHP (*(vu_char *) (CFG_MBAR+0x10002F))
174#define MCFGPIO_PORTJP (*(vu_char *) (CFG_MBAR+0x100030))
175#define MCFGPIO_PORTDDP (*(vu_char *) (CFG_MBAR+0x100031))
176#define MCFGPIO_PORTEHP (*(vu_char *) (CFG_MBAR+0x100032))
177#define MCFGPIO_PORTELP (*(vu_char *) (CFG_MBAR+0x100033))
178#define MCFGPIO_PORTASP (*(vu_char *) (CFG_MBAR+0x100034))
179#define MCFGPIO_PORTQSP (*(vu_char *) (CFG_MBAR+0x100035))
180#define MCFGPIO_PORTSDP (*(vu_char *) (CFG_MBAR+0x100036))
181#define MCFGPIO_PORTTCP (*(vu_char *) (CFG_MBAR+0x100037))
182#define MCFGPIO_PORTTDP (*(vu_char *) (CFG_MBAR+0x100038))
183#define MCFGPIO_PORTUAP (*(vu_char *) (CFG_MBAR+0x100039))
184
185#define MCFGPIO_SETA (*(vu_char *) (CFG_MBAR+0x100028))
186#define MCFGPIO_SETB (*(vu_char *) (CFG_MBAR+0x100029))
187#define MCFGPIO_SETC (*(vu_char *) (CFG_MBAR+0x10002A))
188#define MCFGPIO_SETD (*(vu_char *) (CFG_MBAR+0x10002B))
189#define MCFGPIO_SETE (*(vu_char *) (CFG_MBAR+0x10002C))
190#define MCFGPIO_SETF (*(vu_char *) (CFG_MBAR+0x10002D))
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]191#define MCFGPIO_SETG (*(vu_char *) (CFG_MBAR+0x10002E))
192#define MCFGPIO_SETH (*(vu_char *) (CFG_MBAR+0x10002F))
193#define MCFGPIO_SETJ (*(vu_char *) (CFG_MBAR+0x100030))
194#define MCFGPIO_SETDD (*(vu_char *) (CFG_MBAR+0x100031))
195#define MCFGPIO_SETEH (*(vu_char *) (CFG_MBAR+0x100032))
196#define MCFGPIO_SETEL (*(vu_char *) (CFG_MBAR+0x100033))
197#define MCFGPIO_SETAS (*(vu_char *) (CFG_MBAR+0x100034))
198#define MCFGPIO_SETQS (*(vu_char *) (CFG_MBAR+0x100035))
199#define MCFGPIO_SETSD (*(vu_char *) (CFG_MBAR+0x100036))
200#define MCFGPIO_SETTC (*(vu_char *) (CFG_MBAR+0x100037))
201#define MCFGPIO_SETTD (*(vu_char *) (CFG_MBAR+0x100038))
202#define MCFGPIO_SETUA (*(vu_char *) (CFG_MBAR+0x100039))
Heiko Schocherac1956e2006-04-20 08:42:42 +0200[diff] [blame]203
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]204#define MCFGPIO_CLRA (*(vu_char *) (CFG_MBAR+0x10003C))
205#define MCFGPIO_CLRB (*(vu_char *) (CFG_MBAR+0x10003D))
206#define MCFGPIO_CLRC (*(vu_char *) (CFG_MBAR+0x10003E))
207#define MCFGPIO_CLRD (*(vu_char *) (CFG_MBAR+0x10003F))
208#define MCFGPIO_CLRE (*(vu_char *) (CFG_MBAR+0x100040))
209#define MCFGPIO_CLRF (*(vu_char *) (CFG_MBAR+0x100041))
210#define MCFGPIO_CLRG (*(vu_char *) (CFG_MBAR+0x100042))
211#define MCFGPIO_CLRH (*(vu_char *) (CFG_MBAR+0x100043))
212#define MCFGPIO_CLRJ (*(vu_char *) (CFG_MBAR+0x100044))
213#define MCFGPIO_CLRDD (*(vu_char *) (CFG_MBAR+0x100045))
214#define MCFGPIO_CLREH (*(vu_char *) (CFG_MBAR+0x100046))
215#define MCFGPIO_CLREL (*(vu_char *) (CFG_MBAR+0x100047))
216#define MCFGPIO_CLRAS (*(vu_char *) (CFG_MBAR+0x100048))
217#define MCFGPIO_CLRQS (*(vu_char *) (CFG_MBAR+0x100049))
218#define MCFGPIO_CLRSD (*(vu_char *) (CFG_MBAR+0x10004A))
219#define MCFGPIO_CLRTC (*(vu_char *) (CFG_MBAR+0x10004B))
220#define MCFGPIO_CLRTD (*(vu_char *) (CFG_MBAR+0x10004C))
221#define MCFGPIO_CLRUA (*(vu_char *) (CFG_MBAR+0x10004D))
Heiko Schocherac1956e2006-04-20 08:42:42 +0200[diff] [blame]222
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]223#define MCFGPIO_PBCDPAR (*(vu_char *) (CFG_MBAR+0x100050))
224#define MCFGPIO_PFPAR (*(vu_char *) (CFG_MBAR+0x100051))
225#define MCFGPIO_PEPAR (*(vu_short *)(CFG_MBAR+0x100052))
226#define MCFGPIO_PJPAR (*(vu_char *) (CFG_MBAR+0x100054))
227#define MCFGPIO_PSDPAR (*(vu_char *) (CFG_MBAR+0x100055))
228#define MCFGPIO_PASPAR (*(vu_short *)(CFG_MBAR+0x100056))
229#define MCFGPIO_PEHLPAR (*(vu_char *) (CFG_MBAR+0x100058))
230#define MCFGPIO_PQSPAR (*(vu_char *) (CFG_MBAR+0x100059))
231#define MCFGPIO_PTCPAR (*(vu_char *) (CFG_MBAR+0x10005A))
232#define MCFGPIO_PTDPAR (*(vu_char *) (CFG_MBAR+0x10005B))
233#define MCFGPIO_PUAPAR (*(vu_char *) (CFG_MBAR+0x10005C))
Heiko Schocherac1956e2006-04-20 08:42:42 +0200[diff] [blame]234
235/* Bit level definitions and macros */
236#define MCFGPIO_PORT7 (0x80)
237#define MCFGPIO_PORT6 (0x40)
238#define MCFGPIO_PORT5 (0x20)
239#define MCFGPIO_PORT4 (0x10)
240#define MCFGPIO_PORT3 (0x08)
241#define MCFGPIO_PORT2 (0x04)
242#define MCFGPIO_PORT1 (0x02)
243#define MCFGPIO_PORT0 (0x01)
244#define MCFGPIO_PORT(x) (0x01<<x)
245
246#define MCFGPIO_DDR7 (0x80)
247#define MCFGPIO_DDR6 (0x40)
248#define MCFGPIO_DDR5 (0x20)
249#define MCFGPIO_DDR4 (0x10)
250#define MCFGPIO_DDR3 (0x08)
251#define MCFGPIO_DDR2 (0x04)
252#define MCFGPIO_DDR1 (0x02)
253#define MCFGPIO_DDR0 (0x01)
254#define MCFGPIO_DDR(x) (0x01<<x)
255
256#define MCFGPIO_Px7 (0x80)
257#define MCFGPIO_Px6 (0x40)
258#define MCFGPIO_Px5 (0x20)
259#define MCFGPIO_Px4 (0x10)
260#define MCFGPIO_Px3 (0x08)
261#define MCFGPIO_Px2 (0x04)
262#define MCFGPIO_Px1 (0x02)
263#define MCFGPIO_Px0 (0x01)
264#define MCFGPIO_Px(x) (0x01<<x)
265
Heiko Schocherac1956e2006-04-20 08:42:42 +0200[diff] [blame]266#define MCFGPIO_PBCDPAR_PBPA (0x80)
267#define MCFGPIO_PBCDPAR_PCDPA (0x40)
268
269#define MCFGPIO_PEPAR_PEPA7 (0x4000)
270#define MCFGPIO_PEPAR_PEPA6 (0x1000)
271#define MCFGPIO_PEPAR_PEPA5 (0x0400)
272#define MCFGPIO_PEPAR_PEPA4 (0x0100)
273#define MCFGPIO_PEPAR_PEPA3 (0x0040)
274#define MCFGPIO_PEPAR_PEPA2 (0x0010)
275#define MCFGPIO_PEPAR_PEPA1(x) (((x)&0x3)<<2)
276#define MCFGPIO_PEPAR_PEPA0(x) (((x)&0x3))
277
278#define MCFGPIO_PFPAR_PFPA7 (0x80)
279#define MCFGPIO_PFPAR_PFPA6 (0x40)
280#define MCFGPIO_PFPAR_PFPA5 (0x20)
281
282#define MCFGPIO_PJPAR_PJPA7 (0x80)
283#define MCFGPIO_PJPAR_PJPA6 (0x40)
284#define MCFGPIO_PJPAR_PJPA5 (0x20)
285#define MCFGPIO_PJPAR_PJPA4 (0x10)
286#define MCFGPIO_PJPAR_PJPA3 (0x08)
287#define MCFGPIO_PJPAR_PJPA2 (0x04)
288#define MCFGPIO_PJPAR_PJPA1 (0x02)
289#define MCFGPIO_PJPAR_PJPA0 (0x01)
290#define MCFGPIO_PJPAR_PJPA(x) (0x01<<x)
291
292#define MCFGPIO_PSDPAR_PSDPA (0x80)
293
294#define MCFGPIO_PASPAR_PASPA5(x) (((x)&0x3)<<10)
295#define MCFGPIO_PASPAR_PASPA4(x) (((x)&0x3)<<8)
296#define MCFGPIO_PASPAR_PASPA3(x) (((x)&0x3)<<6)
297#define MCFGPIO_PASPAR_PASPA2(x) (((x)&0x3)<<4)
298#define MCFGPIO_PASPAR_PASPA1(x) (((x)&0x3)<<2)
299#define MCFGPIO_PASPAR_PASPA0(x) (((x)&0x3))
300
301#define MCFGPIO_PEHLPAR_PEHPA (0x80)
302#define MCFGPIO_PEHLPAR_PELPA (0x40)
303
304#define MCFGPIO_PQSPAR_PQSPA6 (0x40)
305#define MCFGPIO_PQSPAR_PQSPA5 (0x20)
306#define MCFGPIO_PQSPAR_PQSPA4 (0x10)
307#define MCFGPIO_PQSPAR_PQSPA3 (0x08)
308#define MCFGPIO_PQSPAR_PQSPA2 (0x04)
309#define MCFGPIO_PQSPAR_PQSPA1 (0x02)
310#define MCFGPIO_PQSPAR_PQSPA0 (0x01)
311#define MCFGPIO_PQSPAR_PQSPA(x) (0x01<<x)
312
313#define MCFGPIO_PTCPAR_PTCPA3(x) (((x)&0x3)<<6)
314#define MCFGPIO_PTCPAR_PTCPA2(x) (((x)&0x3)<<4)
315#define MCFGPIO_PTCPAR_PTCPA1(x) (((x)&0x3)<<2)
316#define MCFGPIO_PTCPAR_PTCPA0(x) (((x)&0x3))
317
318#define MCFGPIO_PTDPAR_PTDPA3(x) (((x)&0x3)<<6)
319#define MCFGPIO_PTDPAR_PTDPA2(x) (((x)&0x3)<<4)
320#define MCFGPIO_PTDPAR_PTDPA1(x) (((x)&0x3)<<2)
321#define MCFGPIO_PTDPAR_PTDPA0(x) (((x)&0x3))
322
323#define MCFGPIO_PUAPAR_PUAPA3 (0x08)
324#define MCFGPIO_PUAPAR_PUAPA2 (0x04)
325#define MCFGPIO_PUAPAR_PUAPA1 (0x02)
326#define MCFGPIO_PUAPAR_PUAPA0 (0x01)
327
328/* System Conrol Module SCM */
329
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]330#define MCFSCM_RAMBAR (*(vu_long *) (CFG_MBAR+0x00000008))
Heiko Schocherac1956e2006-04-20 08:42:42 +0200[diff] [blame]331#define MCFSCM_CRSR (*(vu_char *) (CFG_MBAR+0x00000010))
332#define MCFSCM_CWCR (*(vu_char *) (CFG_MBAR+0x00000011))
333#define MCFSCM_LPICR (*(vu_char *) (CFG_MBAR+0x00000012))
334#define MCFSCM_CWSR (*(vu_char *) (CFG_MBAR+0x00000013))
335
336#define MCFSCM_MPARK (*(vu_long *) (CFG_MBAR+0x0000001C))
337#define MCFSCM_MPR (*(vu_char *) (CFG_MBAR+0x00000020))
338#define MCFSCM_PACR0 (*(vu_char *) (CFG_MBAR+0x00000024))
339#define MCFSCM_PACR1 (*(vu_char *) (CFG_MBAR+0x00000025))
340#define MCFSCM_PACR2 (*(vu_char *) (CFG_MBAR+0x00000026))
341#define MCFSCM_PACR3 (*(vu_char *) (CFG_MBAR+0x00000027))
342#define MCFSCM_PACR4 (*(vu_char *) (CFG_MBAR+0x00000028))
343#define MCFSCM_PACR5 (*(vu_char *) (CFG_MBAR+0x0000002A))
344#define MCFSCM_PACR6 (*(vu_char *) (CFG_MBAR+0x0000002B))
345#define MCFSCM_PACR7 (*(vu_char *) (CFG_MBAR+0x0000002C))
346#define MCFSCM_PACR8 (*(vu_char *) (CFG_MBAR+0x0000002E))
347#define MCFSCM_GPACR0 (*(vu_char *) (CFG_MBAR+0x00000030))
348#define MCFSCM_GPACR1 (*(vu_char *) (CFG_MBAR+0x00000031))
349
Heiko Schocherac1956e2006-04-20 08:42:42 +0200[diff] [blame]350#define MCFSCM_CRSR_EXT (0x80)
351#define MCFSCM_CRSR_CWDR (0x20)
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]352#define MCFSCM_RAMBAR_BA(x) ((x)&0xFFFF0000)
353#define MCFSCM_RAMBAR_BDE (0x00000200)
Heiko Schocherac1956e2006-04-20 08:42:42 +0200[diff] [blame]354
355/* Reset Controller Module RCM */
356
357#define MCFRESET_RCR (*(vu_char *) (CFG_MBAR+0x00110000))
358#define MCFRESET_RSR (*(vu_char *) (CFG_MBAR+0x00110001))
359
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]360#define MCFRESET_RCR_SOFTRST (0x80)
361#define MCFRESET_RCR_FRCRSTOUT (0x40)
362#define MCFRESET_RCR_LVDF (0x10)
363#define MCFRESET_RCR_LVDIE (0x08)
364#define MCFRESET_RCR_LVDRE (0x04)
365#define MCFRESET_RCR_LVDE (0x01)
Heiko Schocherac1956e2006-04-20 08:42:42 +0200[diff] [blame]366
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]367#define MCFRESET_RSR_LVD (0x40)
368#define MCFRESET_RSR_SOFT (0x20)
369#define MCFRESET_RSR_WDR (0x10)
370#define MCFRESET_RSR_POR (0x08)
371#define MCFRESET_RSR_EXT (0x04)
372#define MCFRESET_RSR_LOC (0x02)
373#define MCFRESET_RSR_LOL (0x01)
374#define MCFRESET_RSR_ALL (0x7F)
375#define MCFRESET_RCR_SOFTRST (0x80)
376#define MCFRESET_RCR_FRCRSTOUT (0x40)
Heiko Schocherac1956e2006-04-20 08:42:42 +0200[diff] [blame]377
378/* Chip Configuration Module CCM */
379
380#define MCFCCM_CCR (*(vu_short *)(CFG_MBAR+0x00110004))
381#define MCFCCM_RCON (*(vu_short *)(CFG_MBAR+0x00110008))
382#define MCFCCM_CIR (*(vu_short *)(CFG_MBAR+0x0011000A))
383
Heiko Schocherac1956e2006-04-20 08:42:42 +0200[diff] [blame]384/* Bit level definitions and macros */
385#define MCFCCM_CCR_LOAD (0x8000)
386#define MCFCCM_CCR_MODE(x) (((x)&0x0007)<<8)
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]387#define MCFCCM_CCR_SZEN (0x0040)
388#define MCFCCM_CCR_PSTEN (0x0020)
Heiko Schocherac1956e2006-04-20 08:42:42 +0200[diff] [blame]389#define MCFCCM_CCR_BME (0x0008)
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]390#define MCFCCM_CCR_BMT(x) (((x)&0x0007))
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]391
Heiko Schocherac1956e2006-04-20 08:42:42 +0200[diff] [blame]392#define MCFCCM_CIR_PIN_MASK (0xFF00)
393#define MCFCCM_CIR_PRN_MASK (0x00FF)
394
395/* Clock Module */
396
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]397#define MCFCLOCK_SYNCR (*(vu_short *)(CFG_MBAR+0x120000))
398#define MCFCLOCK_SYNSR (*(vu_char *) (CFG_MBAR+0x120002))
Heiko Schocherac1956e2006-04-20 08:42:42 +0200[diff] [blame]399
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]400#define MCFCLOCK_SYNCR_MFD(x) (((x)&0x0007)<<12)
401#define MCFCLOCK_SYNCR_RFD(x) (((x)&0x0007)<<8)
402#define MCFCLOCK_SYNSR_LOCK 0x08
Heiko Schocherac1956e2006-04-20 08:42:42 +0200[diff] [blame]403
404#define MCFSDRAMC_DCR (*(vu_short *)(CFG_MBAR+0x00000040))
405#define MCFSDRAMC_DACR0 (*(vu_long *) (CFG_MBAR+0x00000048))
406#define MCFSDRAMC_DMR0 (*(vu_long *) (CFG_MBAR+0x0000004c))
407#define MCFSDRAMC_DACR1 (*(vu_long *) (CFG_MBAR+0x00000050))
408#define MCFSDRAMC_DMR1 (*(vu_long *) (CFG_MBAR+0x00000054))
409
410#define MCFSDRAMC_DCR_NAM (0x2000)
411#define MCFSDRAMC_DCR_COC (0x1000)
412#define MCFSDRAMC_DCR_IS (0x0800)
413#define MCFSDRAMC_DCR_RTIM_3 (0x0000)
414#define MCFSDRAMC_DCR_RTIM_6 (0x0200)
415#define MCFSDRAMC_DCR_RTIM_9 (0x0400)
416#define MCFSDRAMC_DCR_RC(x) ((x)&0x01FF)
417
418#define MCFSDRAMC_DACR_BASE(x) ((x)&0xFFFC0000)
419#define MCFSDRAMC_DACR_RE (0x00008000)
420#define MCFSDRAMC_DACR_CASL(x) (((x)&0x03)<<12)
421#define MCFSDRAMC_DACR_CBM(x) (((x)&0x07)<<8)
422#define MCFSDRAMC_DACR_PS_32 (0x00000000)
423#define MCFSDRAMC_DACR_PS_16 (0x00000020)
424#define MCFSDRAMC_DACR_PS_8 (0x00000010)
425#define MCFSDRAMC_DACR_IP (0x00000008)
426#define MCFSDRAMC_DACR_IMRS (0x00000040)
427
428#define MCFSDRAMC_DMR_BAM_16M (0x00FC0000)
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]429#define MCFSDRAMC_DMR_WP (0x00000100)
430#define MCFSDRAMC_DMR_CI (0x00000040)
431#define MCFSDRAMC_DMR_AM (0x00000020)
432#define MCFSDRAMC_DMR_SC (0x00000010)
433#define MCFSDRAMC_DMR_SD (0x00000008)
434#define MCFSDRAMC_DMR_UC (0x00000004)
435#define MCFSDRAMC_DMR_UD (0x00000002)
436#define MCFSDRAMC_DMR_V (0x00000001)
Heiko Schocherac1956e2006-04-20 08:42:42 +0200[diff] [blame]437
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]438#define MCFWTM_WCR (*(vu_short *)(CFG_MBAR+0x00140000))
439#define MCFWTM_WMR (*(vu_short *)(CFG_MBAR+0x00140002))
440#define MCFWTM_WCNTR (*(vu_short *)(CFG_MBAR+0x00140004))
441#define MCFWTM_WSR (*(vu_short *)(CFG_MBAR+0x00140006))
Heiko Schocherac1956e2006-04-20 08:42:42 +0200[diff] [blame]442
443/* Chip SELECT Module CSM */
444#define MCFCSM_CSAR0 (*(vu_short *)(CFG_MBAR+0x00000080))
445#define MCFCSM_CSMR0 (*(vu_long *) (CFG_MBAR+0x00000084))
446#define MCFCSM_CSCR0 (*(vu_short *)(CFG_MBAR+0x0000008a))
447#define MCFCSM_CSAR1 (*(vu_short *)(CFG_MBAR+0x0000008C))
448#define MCFCSM_CSMR1 (*(vu_long *) (CFG_MBAR+0x00000090))
449#define MCFCSM_CSCR1 (*(vu_short *)(CFG_MBAR+0x00000096))
450#define MCFCSM_CSAR2 (*(vu_short *)(CFG_MBAR+0x00000098))
451#define MCFCSM_CSMR2 (*(vu_long *) (CFG_MBAR+0x0000009C))
452#define MCFCSM_CSCR2 (*(vu_short *)(CFG_MBAR+0x000000A2))
453#define MCFCSM_CSAR3 (*(vu_short *)(CFG_MBAR+0x000000A4))
454#define MCFCSM_CSMR3 (*(vu_long *) (CFG_MBAR+0x000000A8))
455#define MCFCSM_CSCR3 (*(vu_short *)(CFG_MBAR+0x000000AE))
456
457#define MCFCSM_CSMR_BAM(x) ((x) & 0xFFFF0000)
458#define MCFCSM_CSMR_WP (1<<8)
459#define MCFCSM_CSMR_V (0x01)
460#define MCFCSM_CSCR_WS(x) ((x & 0x0F)<<10)
461#define MCFCSM_CSCR_AA (0x0100)
462#define MCFCSM_CSCR_PS_32 (0x0000)
463#define MCFCSM_CSCR_PS_8 (0x0040)
464#define MCFCSM_CSCR_PS_16 (0x0080)
465
466/*********************************************************************
Heiko Schocherac1956e2006-04-20 08:42:42 +0200[diff] [blame]467* General Purpose Timer (GPT) Module
Heiko Schocherac1956e2006-04-20 08:42:42 +0200[diff] [blame]468*********************************************************************/
469
470#define MCFGPTA_GPTIOS (*(vu_char *)(CFG_MBAR+0x1A0000))
471#define MCFGPTA_GPTCFORC (*(vu_char *)(CFG_MBAR+0x1A0001))
472#define MCFGPTA_GPTOC3M (*(vu_char *)(CFG_MBAR+0x1A0002))
473#define MCFGPTA_GPTOC3D (*(vu_char *)(CFG_MBAR+0x1A0003))
474#define MCFGPTA_GPTCNT (*(vu_short *)(CFG_MBAR+0x1A0004))
475#define MCFGPTA_GPTSCR1 (*(vu_char *)(CFG_MBAR+0x1A0006))
476#define MCFGPTA_GPTTOV (*(vu_char *)(CFG_MBAR+0x1A0008))
477#define MCFGPTA_GPTCTL1 (*(vu_char *)(CFG_MBAR+0x1A0009))
478#define MCFGPTA_GPTCTL2 (*(vu_char *)(CFG_MBAR+0x1A000B))
479#define MCFGPTA_GPTIE (*(vu_char *)(CFG_MBAR+0x1A000C))
480#define MCFGPTA_GPTSCR2 (*(vu_char *)(CFG_MBAR+0x1A000D))
481#define MCFGPTA_GPTFLG1 (*(vu_char *)(CFG_MBAR+0x1A000E))
482#define MCFGPTA_GPTFLG2 (*(vu_char *)(CFG_MBAR+0x1A000F))
483#define MCFGPTA_GPTC0 (*(vu_short *)(CFG_MBAR+0x1A0010))
484#define MCFGPTA_GPTC1 (*(vu_short *)(CFG_MBAR+0x1A0012))
485#define MCFGPTA_GPTC2 (*(vu_short *)(CFG_MBAR+0x1A0014))
486#define MCFGPTA_GPTC3 (*(vu_short *)(CFG_MBAR+0x1A0016))
487#define MCFGPTA_GPTPACTL (*(vu_char *)(CFG_MBAR+0x1A0018))
488#define MCFGPTA_GPTPAFLG (*(vu_char *)(CFG_MBAR+0x1A0019))
489#define MCFGPTA_GPTPACNT (*(vu_short *)(CFG_MBAR+0x1A001A))
490#define MCFGPTA_GPTPORT (*(vu_char *)(CFG_MBAR+0x1A001D))
491#define MCFGPTA_GPTDDR (*(vu_char *)(CFG_MBAR+0x1A001E))
492
Heiko Schocherac1956e2006-04-20 08:42:42 +0200[diff] [blame]493#define MCFGPTB_GPTIOS (*(vu_char *)(CFG_MBAR+0x1B0000))
494#define MCFGPTB_GPTCFORC (*(vu_char *)(CFG_MBAR+0x1B0001))
495#define MCFGPTB_GPTOC3M (*(vu_char *)(CFG_MBAR+0x1B0002))
496#define MCFGPTB_GPTOC3D (*(vu_char *)(CFG_MBAR+0x1B0003))
497#define MCFGPTB_GPTCNT (*(vu_short *)(CFG_MBAR+0x1B0004))
498#define MCFGPTB_GPTSCR1 (*(vu_char *)(CFG_MBAR+0x1B0006))
499#define MCFGPTB_GPTTOV (*(vu_char *)(CFG_MBAR+0x1B0008))
500#define MCFGPTB_GPTCTL1 (*(vu_char *)(CFG_MBAR+0x1B0009))
501#define MCFGPTB_GPTCTL2 (*(vu_char *)(CFG_MBAR+0x1B000B))
502#define MCFGPTB_GPTIE (*(vu_char *)(CFG_MBAR+0x1B000C))
503#define MCFGPTB_GPTSCR2 (*(vu_char *)(CFG_MBAR+0x1B000D))
504#define MCFGPTB_GPTFLG1 (*(vu_char *)(CFG_MBAR+0x1B000E))
505#define MCFGPTB_GPTFLG2 (*(vu_char *)(CFG_MBAR+0x1B000F))
506#define MCFGPTB_GPTC0 (*(vu_short *)(CFG_MBAR+0x1B0010))
507#define MCFGPTB_GPTC1 (*(vu_short *)(CFG_MBAR+0x1B0012))
508#define MCFGPTB_GPTC2 (*(vu_short *)(CFG_MBAR+0x1B0014))
509#define MCFGPTB_GPTC3 (*(vu_short *)(CFG_MBAR+0x1B0016))
510#define MCFGPTB_GPTPACTL (*(vu_char *)(CFG_MBAR+0x1B0018))
511#define MCFGPTB_GPTPAFLG (*(vu_char *)(CFG_MBAR+0x1B0019))
512#define MCFGPTB_GPTPACNT (*(vu_short *)(CFG_MBAR+0x1B001A))
513#define MCFGPTB_GPTPORT (*(vu_char *)(CFG_MBAR+0x1B001D))
514#define MCFGPTB_GPTDDR (*(vu_char *)(CFG_MBAR+0x1B001E))
515
516/* Bit level definitions and macros */
517#define MCFGPT_GPTIOS_IOS3 (0x08)
518#define MCFGPT_GPTIOS_IOS2 (0x04)
519#define MCFGPT_GPTIOS_IOS1 (0x02)
520#define MCFGPT_GPTIOS_IOS0 (0x01)
521
522#define MCFGPT_GPTCFORC_FOC3 (0x08)
523#define MCFGPT_GPTCFORC_FOC2 (0x04)
524#define MCFGPT_GPTCFORC_FOC1 (0x02)
525#define MCFGPT_GPTCFORC_FOC0 (0x01)
526
527#define MCFGPT_GPTOC3M_OC3M3 (0x08)
528#define MCFGPT_GPTOC3M_OC3M2 (0x04)
529#define MCFGPT_GPTOC3M_OC3M1 (0x02)
530#define MCFGPT_GPTOC3M_OC3M0 (0x01)
531
532#define MCFGPT_GPTOC3M_OC3D(x) (((x)&0x04))
533
534#define MCFGPT_GPTSCR1_GPTEN (0x80)
535#define MCFGPT_GPTSCR1_TFFCA (0x10)
536
537#define MCFGPT_GPTTOV3 (0x08)
538#define MCFGPT_GPTTOV2 (0x04)
539#define MCFGPT_GPTTOV1 (0x02)
540#define MCFGPT_GPTTOV0 (0x01)
541
542#define MCFGPT_GPTCTL_OMOL3(x) (((x)&0x03)<<6)
543#define MCFGPT_GPTCTL_OMOL2(x) (((x)&0x03)<<4)
544#define MCFGPT_GPTCTL_OMOL1(x) (((x)&0x03)<<2)
545#define MCFGPT_GPTCTL_OMOL0(x) (((x)&0x03))
546
547#define MCFGPT_GPTCTL2_EDG3(x) (((x)&0x03)<<6)
548#define MCFGPT_GPTCTL2_EDG2(x) (((x)&0x03)<<4)
549#define MCFGPT_GPTCTL2_EDG1(x) (((x)&0x03)<<2)
550#define MCFGPT_GPTCTL2_EDG0(x) (((x)&0x03))
551
552#define MCFGPT_GPTIE_C3I (0x08)
553#define MCFGPT_GPTIE_C2I (0x04)
554#define MCFGPT_GPTIE_C1I (0x02)
555#define MCFGPT_GPTIE_C0I (0x01)
556
557#define MCFGPT_GPTSCR2_TOI (0x80)
558#define MCFGPT_GPTSCR2_PUPT (0x20)
559#define MCFGPT_GPTSCR2_RDPT (0x10)
560#define MCFGPT_GPTSCR2_TCRE (0x08)
561#define MCFGPT_GPTSCR2_PR(x) (((x)&0x07))
562
563#define MCFGPT_GPTFLG1_C3F (0x08)
564#define MCFGPT_GPTFLG1_C2F (0x04)
565#define MCFGPT_GPTFLG1_C1F (0x02)
566#define MCFGPT_GPTFLG1_C0F (0x01)
567
568#define MCFGPT_GPTFLG2_TOF (0x80)
569#define MCFGPT_GPTFLG2_C3F (0x08)
570#define MCFGPT_GPTFLG2_C2F (0x04)
571#define MCFGPT_GPTFLG2_C1F (0x02)
572#define MCFGPT_GPTFLG2_C0F (0x01)
573
574#define MCFGPT_GPTPACTL_PAE (0x40)
575#define MCFGPT_GPTPACTL_PAMOD (0x20)
576#define MCFGPT_GPTPACTL_PEDGE (0x10)
577#define MCFGPT_GPTPACTL_CLK_PACLK (0x04)
578#define MCFGPT_GPTPACTL_CLK_PACLK256 (0x08)
579#define MCFGPT_GPTPACTL_CLK_PACLK65536 (0x0C)
580#define MCFGPT_GPTPACTL_CLK(x) (((x)&0x03)<<2)
581#define MCFGPT_GPTPACTL_PAOVI (0x02)
582#define MCFGPT_GPTPACTL_PAI (0x01)
583
584#define MCFGPT_GPTPAFLG_PAOVF (0x02)
585#define MCFGPT_GPTPAFLG_PAIF (0x01)
586
587#define MCFGPT_GPTPORT_PORTT3 (0x08)
588#define MCFGPT_GPTPORT_PORTT2 (0x04)
589#define MCFGPT_GPTPORT_PORTT1 (0x02)
590#define MCFGPT_GPTPORT_PORTT0 (0x01)
591
592#define MCFGPT_GPTDDR_DDRT3 (0x08)
593#define MCFGPT_GPTDDR_DDRT2 (0x04)
594#define MCFGPT_GPTDDR_DDRT1 (0x02)
595#define MCFGPT_GPTDDR_DDRT0 (0x01)
596
597/* Coldfire Flash Module CFM */
598
599#define MCFCFM_MCR (*(vu_short *)(CFG_MBAR+0x1D0000))
600#define MCFCFM_MCR_LOCK (0x0400)
601#define MCFCFM_MCR_PVIE (0x0200)
602#define MCFCFM_MCR_AEIE (0x0100)
603#define MCFCFM_MCR_CBEIE (0x0080)
604#define MCFCFM_MCR_CCIE (0x0040)
605#define MCFCFM_MCR_KEYACC (0x0020)
606
607#define MCFCFM_CLKD (*(vu_char *)(CFG_MBAR+0x1D0002))
608
609#define MCFCFM_SEC (*(vu_long*) (CFG_MBAR+0x1D0008))
610#define MCFCFM_SEC_KEYEN (0x80000000)
611#define MCFCFM_SEC_SECSTAT (0x40000000)
612
613#define MCFCFM_PROT (*(vu_long*) (CFG_MBAR+0x1D0010))
614#define MCFCFM_SACC (*(vu_long*) (CFG_MBAR+0x1D0014))
615#define MCFCFM_DACC (*(vu_long*) (CFG_MBAR+0x1D0018))
616#define MCFCFM_USTAT (*(vu_char*) (CFG_MBAR+0x1D0020))
617#define MCFCFM_USTAT_CBEIF 0x80
618#define MCFCFM_USTAT_CCIF 0x40
619#define MCFCFM_USTAT_PVIOL 0x20
620#define MCFCFM_USTAT_ACCERR 0x10
621#define MCFCFM_USTAT_BLANK 0x04
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]622
Heiko Schocherac1956e2006-04-20 08:42:42 +0200[diff] [blame]623#define MCFCFM_CMD (*(vu_char*) (CFG_MBAR+0x1D0024))
624#define MCFCFM_CMD_ERSVER 0x05
625#define MCFCFM_CMD_PGERSVER 0x06
626#define MCFCFM_CMD_PGM 0x20
627#define MCFCFM_CMD_PGERS 0x40
628#define MCFCFM_CMD_MASERS 0x41
wdenke65527f2004-02-12 00:47:09 +0000[diff] [blame]629
630/****************************************************************************/
TsiChungLiew0e81abc2007-08-15 19:38:15 -0500[diff] [blame]631#endif /* m5282_h */