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git01.mediatek.com / filogic / uboot / 3b74ccfebc4885f98a06e0a24f558638c9347562 / . / include / configs / bf548-ezkit.h
blob: 9376283ffcbe942a2700144197e5b2069ac20fc3 [file] [log] [blame]
Mike Frysinger979294f2008-10-12 05:05:42 -0400[diff] [blame]1/*
Bin Meng75574052016-02-05 19:30:11 -0800[diff] [blame]2 * U-Boot - Configuration file for BF548 STAMP board
Mike Frysinger979294f2008-10-12 05:05:42 -0400[diff] [blame]3 */
4
5#ifndef __CONFIG_BF548_EZKIT_H__
6#define __CONFIG_BF548_EZKIT_H__
7
Mike Frysinger18a407c2009-04-24 17:22:40 -0400[diff] [blame]8#include <asm/config-pre.h>
Mike Frysinger979294f2008-10-12 05:05:42 -0400[diff] [blame]9
Mike Frysinger979294f2008-10-12 05:05:42 -0400[diff] [blame]10/*
11 * Processor Settings
12 */
Mike Frysinger5b0c1282010-12-23 14:58:37 -0500[diff] [blame]13#define CONFIG_BFIN_CPU bf548-0.0
Mike Frysinger979294f2008-10-12 05:05:42 -0400[diff] [blame]14#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA
15
Mike Frysinger979294f2008-10-12 05:05:42 -0400[diff] [blame]16/*
17 * Clock Settings
18 * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
19 * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
20 */
21/* CONFIG_CLKIN_HZ is any value in Hz */
22#define CONFIG_CLKIN_HZ 25000000
23/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
24/* 1 = CLKIN / 2 */
25#define CONFIG_CLKIN_HALF 0
26/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
27/* 1 = bypass PLL */
28#define CONFIG_PLL_BYPASS 0
29/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
30/* Values can range from 0-63 (where 0 means 64) */
31#define CONFIG_VCO_MULT 21
32/* CCLK_DIV controls the core clock divider */
33/* Values can be 1, 2, 4, or 8 ONLY */
34#define CONFIG_CCLK_DIV 1
35/* SCLK_DIV controls the system clock divider */
36/* Values can range from 1-15 */
37#define CONFIG_SCLK_DIV 4
38
Mike Frysinger979294f2008-10-12 05:05:42 -0400[diff] [blame]39/*
40 * Memory Settings
41 */
42#define CONFIG_MEM_ADD_WDTH 10
43#define CONFIG_MEM_SIZE 64
44
45#define CONFIG_EBIU_DDRCTL0_VAL 0x218A83FE
46#define CONFIG_EBIU_DDRCTL1_VAL 0x20022222
47#define CONFIG_EBIU_DDRCTL2_VAL 0x00000021
48
49/* Default EZ-Kit bank mapping:
50 * Async Bank 0 - 32MB Burst Flash
51 * Async Bank 1 - Ethernet
52 * Async Bank 2 - Nothing
53 * Async Bank 3 - Nothing
54 */
55#define CONFIG_EBIU_AMGCTL_VAL 0xFF
56#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
57#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
58#define CONFIG_EBIU_FCTL_VAL (BCLK_4)
59#define CONFIG_EBIU_MODE_VAL (B0MODE_FLASH)
60
Mike Frysingera2306572009-06-14 21:23:27 -0400[diff] [blame]61#define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
Mike Frysinger979294f2008-10-12 05:05:42 -0400[diff] [blame]62#define CONFIG_SYS_MALLOC_LEN (768 * 1024)
63
Mike Frysinger979294f2008-10-12 05:05:42 -0400[diff] [blame]64/*
65 * Network Settings
66 */
67#define ADI_CMDS_NETWORK 1
Ben Warrenfbfdd3a2009-07-20 22:01:11 -0700[diff] [blame]68#define CONFIG_SMC911X 1
69#define CONFIG_SMC911X_BASE 0x24000000
70#define CONFIG_SMC911X_16_BIT
Mike Frysinger979294f2008-10-12 05:05:42 -0400[diff] [blame]71#define CONFIG_HOSTNAME bf548-ezkit
Mike Frysinger979294f2008-10-12 05:05:42 -0400[diff] [blame]72
Mike Frysinger979294f2008-10-12 05:05:42 -0400[diff] [blame]73/*
74 * Flash Settings
75 */
76#define CONFIG_FLASH_CFI_DRIVER
77#define CONFIG_SYS_FLASH_BASE 0x20000000
78#define CONFIG_SYS_FLASH_CFI
79#define CONFIG_SYS_FLASH_PROTECTION
80#define CONFIG_SYS_MAX_FLASH_BANKS 1
81#define CONFIG_SYS_MAX_FLASH_SECT 259
82
Mike Frysinger979294f2008-10-12 05:05:42 -0400[diff] [blame]83/*
84 * SPI Settings
85 */
86#define CONFIG_BFIN_SPI
87#define CONFIG_ENV_SPI_MAX_HZ 30000000
Mike Frysinger9a4406462009-06-14 22:29:35 -0400[diff] [blame]88#define CONFIG_SF_DEFAULT_SPEED 30000000
Mike Frysinger979294f2008-10-12 05:05:42 -0400[diff] [blame]89
Mike Frysinger979294f2008-10-12 05:05:42 -0400[diff] [blame]90/*
91 * Env Storage Settings
92 */
93#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
94#define CONFIG_ENV_IS_IN_SPI_FLASH
95#define CONFIG_ENV_OFFSET 0x10000
96#define CONFIG_ENV_SIZE 0x2000
97#define CONFIG_ENV_SECT_SIZE 0x10000
Mike Frysinger45b57bd2009-07-21 22:17:36 -0400[diff] [blame]98#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
Mike Frysinger979294f2008-10-12 05:05:42 -0400[diff] [blame]99#elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND)
100#define CONFIG_ENV_IS_IN_NAND
Mike Frysinger03ecad82011-03-17 17:07:47 -0400[diff] [blame]101#define CONFIG_ENV_OFFSET 0x60000
Mike Frysinger979294f2008-10-12 05:05:42 -0400[diff] [blame]102#define CONFIG_ENV_SIZE 0x20000
103#else
Mike Frysingerba31b832011-05-09 15:43:27 -0400[diff] [blame]104/* The BF548-EZKIT uses a top boot flash */
Mike Frysinger979294f2008-10-12 05:05:42 -0400[diff] [blame]105#define CONFIG_ENV_IS_IN_FLASH 1
Mike Frysingerba31b832011-05-09 15:43:27 -0400[diff] [blame]106#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
107#define CONFIG_ENV_OFFSET (0x1000000 - CONFIG_ENV_SECT_SIZE)
108#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
109#define CONFIG_ENV_SECT_SIZE 0x8000
Mike Frysinger979294f2008-10-12 05:05:42 -0400[diff] [blame]110#endif
111
Mike Frysinger979294f2008-10-12 05:05:42 -0400[diff] [blame]112/*
113 * NAND Settings
114 */
Mike Frysinger979294f2008-10-12 05:05:42 -0400[diff] [blame]115#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND)
Bob Liuec39f222013-02-05 19:22:20 +0800[diff] [blame]116#define CONFIG_BFIN_NFC_CTL_VAL 0x0033
117#define CONFIG_BFIN_NFC_BOOTROM_ECC
Mike Frysinger979294f2008-10-12 05:05:42 -0400[diff] [blame]118#define CONFIG_DRIVER_NAND_BFIN
Bob Liuec39f222013-02-05 19:22:20 +0800[diff] [blame]119#define CONFIG_SYS_NAND_BASE 0 /* not actually used */
120#define CONFIG_SYS_MAX_NAND_DEVICE 1
121#endif
Mike Frysinger979294f2008-10-12 05:05:42 -0400[diff] [blame]122
123/*
124 * I2C Settings
125 */
Scott Jiang80d27fa2014-11-13 15:30:55 +0800[diff] [blame]126#define CONFIG_SYS_I2C
Scott Jiang655761e2014-11-13 15:30:53 +0800[diff] [blame]127#define CONFIG_SYS_I2C_ADI
Mike Frysinger979294f2008-10-12 05:05:42 -0400[diff] [blame]128
Mike Frysinger979294f2008-10-12 05:05:42 -0400[diff] [blame]129/*
130 * SATA
131 */
132#if !defined(__ADSPBF544__)
133#define CONFIG_LIBATA
134#define CONFIG_SYS_SATA_MAX_DEVICE 1
135#define CONFIG_LBA48
136#define CONFIG_PATA_BFIN
137#define CONFIG_BFIN_ATAPI_BASE_ADDR 0xFFC03800
138#define CONFIG_BFIN_ATA_MODE XFER_PIO_4
139#endif
140
Mike Frysinger979294f2008-10-12 05:05:42 -0400[diff] [blame]141/*
142 * SDH Settings
143 */
144#if !defined(__ADSPBF544__)
Cliff Caie4638922009-11-20 08:24:43 +0000[diff] [blame]145#define CONFIG_GENERIC_MMC
Mike Frysinger979294f2008-10-12 05:05:42 -0400[diff] [blame]146#define CONFIG_MMC
147#define CONFIG_BFIN_SDH
148#endif
149
Mike Frysinger979294f2008-10-12 05:05:42 -0400[diff] [blame]150/*
151 * USB Settings
152 */
153#if !defined(__ADSPBF544__)
Paul Kocialkowskif34dfcb2015-08-04 17:04:06 +0200[diff] [blame]154#define CONFIG_USB_MUSB_HCD
Mike Frysinger979294f2008-10-12 05:05:42 -0400[diff] [blame]155#define CONFIG_USB_BLACKFIN
Paul Kocialkowskif34dfcb2015-08-04 17:04:06 +0200[diff] [blame]156#define CONFIG_USB_MUSB_TIMEOUT 100000
Mike Frysinger979294f2008-10-12 05:05:42 -0400[diff] [blame]157#endif
158
Mike Frysinger979294f2008-10-12 05:05:42 -0400[diff] [blame]159/*
160 * Misc Settings
161 */
162#define CONFIG_BOARD_EARLY_INIT_F
Mike Frysingercc64ba62010-10-19 18:02:43 -0400[diff] [blame]163#define CONFIG_BOARD_SIZE_LIMIT $$(( 512 * 1024 ))
Mike Frysinger979294f2008-10-12 05:05:42 -0400[diff] [blame]164#define CONFIG_RTC_BFIN
165#define CONFIG_UART_CONSOLE 1
Mike Frysinger55c5d712010-09-29 20:24:16 +0000[diff] [blame]166#define CONFIG_BFIN_SPI_IMG_SIZE 0x50000
Mike Frysinger979294f2008-10-12 05:05:42 -0400[diff] [blame]167
Sonic Zhang3edc3f32013-05-02 13:46:21 +0800[diff] [blame]168#define CONFIG_ADI_GPIO2
169
Bob Liuec39f222013-02-05 19:22:20 +0800[diff] [blame]170#ifdef CONFIG_VIDEO
171#define EASYLOGO_HEADER < asm/bfin_logo_230x230_gzip.h >
172#define CONFIG_DEB_DMA_URGENT
Mike Frysinger979294f2008-10-12 05:05:42 -0400[diff] [blame]173#endif
174
175/* Define if want to do post memory test */
176#undef CONFIG_POST
177#ifdef CONFIG_POST
Mike Frysinger32ed1fe2011-05-10 16:22:25 -0400[diff] [blame]178#define CONFIG_POST_BSPEC1_GPIO_LEDS \
179 GPIO_PG6, GPIO_PG7, GPIO_PG8, GPIO_PG9, GPIO_PG10, GPIO_PG11,
180#define CONFIG_POST_BSPEC2_GPIO_BUTTONS \
181 GPIO_PB8, GPIO_PB9, GPIO_PB10, GPIO_PB11
182#define CONFIG_POST_BSPEC2_GPIO_NAMES \
183 13, 12, 11, 10,
Mike Frysinger368cfc82011-05-10 16:48:36 -0400[diff] [blame]184#define CONFIG_SYS_POST_FLASH_START 10
185#define CONFIG_SYS_POST_FLASH_END 127
Mike Frysinger979294f2008-10-12 05:05:42 -0400[diff] [blame]186#endif
187
Mike Frysinger979294f2008-10-12 05:05:42 -0400[diff] [blame]188/*
189 * Pull in common ADI header for remaining command/environment setup
190 */
191#include <configs/bfin_adi_common.h>
192
Mike Frysinger979294f2008-10-12 05:05:42 -0400[diff] [blame]193#endif