blob: d4195b45bbd4d5df3f4d8ec5cbdc6121a7def42e [file] [log] [blame]
Simon Glassb2c1cac2014-02-26 15:59:21 -07001/dts-v1/;
2
Patrick Delaunay23aee612020-01-13 11:35:13 +01003#include <dt-bindings/gpio/gpio.h>
4#include <dt-bindings/gpio/sandbox-gpio.h>
Sean Anderson3438e3b2020-09-14 11:01:57 -04005#include <dt-bindings/pinctrl/sandbox-pinmux.h>
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +05306#include <dt-bindings/mux/mux.h>
Patrick Delaunay23aee612020-01-13 11:35:13 +01007
Simon Glassb2c1cac2014-02-26 15:59:21 -07008/ {
9 model = "sandbox";
10 compatible = "sandbox";
11 #address-cells = <1>;
Simon Glasscf61f742015-07-06 12:54:36 -060012 #size-cells = <1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -070013
Simon Glassfef72b72014-07-23 06:55:03 -060014 aliases {
15 console = &uart0;
Simon Glass5b968632015-05-22 15:42:15 -060016 eth0 = "/eth@10002000";
Bin Meng04a11cb2015-08-27 22:25:53 -070017 eth3 = &eth_3;
Simon Glass5b968632015-05-22 15:42:15 -060018 eth5 = &eth_5;
Simon Glass5620cf82018-10-01 12:22:40 -060019 gpio1 = &gpio_a;
20 gpio2 = &gpio_b;
Patrick Delaunay28bdaa52020-01-13 11:35:14 +010021 gpio3 = &gpio_c;
Simon Glass0ccb0972015-01-25 08:27:05 -070022 i2c0 = "/i2c@0";
Simon Glasse4fef742017-04-23 20:02:07 -060023 mmc0 = "/mmc0";
24 mmc1 = "/mmc1";
Bin Meng408e5902018-08-03 01:14:41 -070025 pci0 = &pci0;
26 pci1 = &pci1;
Bin Meng510dddb2018-08-03 01:14:50 -070027 pci2 = &pci2;
Michael Walle7c41a222020-06-02 01:47:09 +020028 remoteproc0 = &rproc_1;
29 remoteproc1 = &rproc_2;
Simon Glass336b2952015-05-22 15:42:17 -060030 rtc0 = &rtc_0;
31 rtc1 = &rtc_1;
Simon Glass5b968632015-05-22 15:42:15 -060032 spi0 = "/spi@0";
Przemyslaw Marczak3dbb55e2015-05-13 13:38:34 +020033 testfdt6 = "/e-test";
Simon Glass0ccb0972015-01-25 08:27:05 -070034 testbus3 = "/some-bus";
35 testfdt0 = "/some-bus/c-test@0";
Simon Glass7d5e4112020-12-16 21:20:26 -070036 testfdt12 = "/some-bus/c-test@1";
Simon Glass0ccb0972015-01-25 08:27:05 -070037 testfdt3 = "/b-test";
38 testfdt5 = "/some-bus/c-test@5";
39 testfdt8 = "/a-test";
Simon Glass791a17f2020-12-16 21:20:27 -070040 testfdtm1 = &testfdtm1;
Eugeniu Rosca5ba71e52018-05-19 14:13:55 +020041 fdt-dummy0 = "/translation-test@8000/dev@0,0";
42 fdt-dummy1 = "/translation-test@8000/dev@1,100";
43 fdt-dummy2 = "/translation-test@8000/dev@2,200";
44 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Dario Binacchib574d682020-12-30 00:16:21 +010045 fdt-dummy4 = "/translation-test@8000/xlatebus@4,400/devs/dev@19";
Simon Glass31680482015-03-25 12:23:05 -060046 usb0 = &usb_0;
47 usb1 = &usb_1;
48 usb2 = &usb_2;
Mario Six95922152018-08-09 14:51:19 +020049 axi0 = &axi;
Mario Six02ad6fb2018-09-27 09:19:31 +020050 osd0 = "/osd";
Simon Glassfef72b72014-07-23 06:55:03 -060051 };
52
Simon Glassed96cde2018-12-10 10:37:33 -070053 audio: audio-codec {
54 compatible = "sandbox,audio-codec";
55 #sound-dai-cells = <1>;
56 };
57
Philippe Reynes1ee26482020-07-24 18:19:51 +020058 buttons {
59 compatible = "gpio-keys";
60
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +020061 btn1 {
Philippe Reynes1ee26482020-07-24 18:19:51 +020062 gpios = <&gpio_a 3 0>;
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +020063 label = "button1";
Philippe Reynes1ee26482020-07-24 18:19:51 +020064 };
65
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +020066 btn2 {
Philippe Reynes1ee26482020-07-24 18:19:51 +020067 gpios = <&gpio_a 4 0>;
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +020068 label = "button2";
Philippe Reynes1ee26482020-07-24 18:19:51 +020069 };
70 };
71
Simon Glassc953aaf2018-12-10 10:37:34 -070072 cros_ec: cros-ec {
Simon Glass699c9ca2018-10-01 12:22:08 -060073 reg = <0 0>;
74 compatible = "google,cros-ec-sandbox";
75
76 /*
77 * This describes the flash memory within the EC. Note
78 * that the STM32L flash erases to 0, not 0xff.
79 */
80 flash {
81 image-pos = <0x08000000>;
82 size = <0x20000>;
83 erase-value = <0>;
84
85 /* Information for sandbox */
86 ro {
87 image-pos = <0>;
88 size = <0xf000>;
89 };
90 wp-ro {
91 image-pos = <0xf000>;
92 size = <0x1000>;
Simon Glassbf0a6922021-01-21 13:57:14 -070093 used = <0x884>;
94 compress = "lz4";
95 uncomp-size = <0xcf8>;
96 hash {
97 algo = "sha256";
98 value = [00 01 02 03 04 05 06 07
99 08 09 0a 0b 0c 0d 0e 0f
100 10 11 12 13 14 15 16 17
101 18 19 1a 1b 1c 1d 1e 1f];
102 };
Simon Glass699c9ca2018-10-01 12:22:08 -0600103 };
104 rw {
105 image-pos = <0x10000>;
106 size = <0x10000>;
107 };
108 };
109 };
110
Yannick Fertré9712c822019-10-07 15:29:05 +0200111 dsi_host: dsi_host {
112 compatible = "sandbox,dsi-host";
113 };
114
Simon Glassb2c1cac2014-02-26 15:59:21 -0700115 a-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600116 reg = <0 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700117 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600118 ping-expect = <0>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700119 ping-add = <0>;
Simon Glassfef72b72014-07-23 06:55:03 -0600120 u-boot,dm-pre-reloc;
Patrick Delaunay23aee612020-01-13 11:35:13 +0100121 test-gpios = <&gpio_a 1>, <&gpio_a 4>,
122 <&gpio_b 5 GPIO_ACTIVE_HIGH 3 2 1>,
Simon Glass16e10402015-01-05 20:05:29 -0700123 <0>, <&gpio_a 12>;
Patrick Delaunay23aee612020-01-13 11:35:13 +0100124 test2-gpios = <&gpio_a 1>, <&gpio_a 4>,
125 <&gpio_b 6 GPIO_ACTIVE_LOW 3 2 1>,
126 <&gpio_b 7 GPIO_IN 3 2 1>,
127 <&gpio_b 8 GPIO_OUT 3 2 1>,
128 <&gpio_b 9 (GPIO_OUT|GPIO_OUT_ACTIVE) 3 2 1>;
Patrick Delaunay28bdaa52020-01-13 11:35:14 +0100129 test3-gpios =
130 <&gpio_c 0 (GPIO_OUT|GPIO_OPEN_DRAIN)>,
131 <&gpio_c 1 (GPIO_OUT|GPIO_OPEN_SOURCE)>,
132 <&gpio_c 2 GPIO_OUT>,
133 <&gpio_c 3 (GPIO_IN|GPIO_PULL_UP)>,
134 <&gpio_c 4 (GPIO_IN|GPIO_PULL_DOWN)>,
Neil Armstrong643778b2020-05-05 10:43:18 +0200135 <&gpio_c 5 GPIO_IN>,
136 <&gpio_c 6 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_DRAIN)>,
137 <&gpio_c 7 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_SOURCE)>;
Jean-Jacques Hiblot73873402020-09-11 13:43:35 +0530138 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
139 test5-gpios = <&gpio_a 19>;
140
Simon Glass6df01f92018-12-10 10:37:37 -0700141 int-value = <1234>;
142 uint-value = <(-1234)>;
Dario Binacchi421e81e2020-03-29 18:04:40 +0200143 int64-value = /bits/ 64 <0x1111222233334444>;
Dario Binacchi81d80b52020-03-29 18:04:41 +0200144 int-array = <5678 9123 4567>;
Simon Glassdd0ed902020-07-07 13:11:58 -0600145 str-value = "test string";
Simon Glass515dcff2020-02-06 09:55:00 -0700146 interrupts-extended = <&irq 3 0>;
Simon Glass09642392020-07-07 13:12:11 -0600147 acpi,name = "GHIJ";
Patrick Delaunay8cd28012020-09-25 09:41:16 +0200148 phandle-value = <&gpio_c 10>, <0xFFFFFFFF 20>, <&gpio_a 30>;
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +0530149
150 mux-controls = <&muxcontroller0 0>, <&muxcontroller0 1>,
151 <&muxcontroller0 2>, <&muxcontroller0 3>,
152 <&muxcontroller1>;
153 mux-control-names = "mux0", "mux1", "mux2", "mux3", "mux4";
154 mux-syscon = <&syscon3>;
Dario Binacchi836cc9d2020-12-30 00:16:26 +0100155 display-timings {
156 timing0: 240x320 {
157 clock-frequency = <6500000>;
158 hactive = <240>;
159 vactive = <320>;
160 hfront-porch = <6>;
161 hback-porch = <7>;
162 hsync-len = <1>;
163 vback-porch = <5>;
164 vfront-porch = <8>;
165 vsync-len = <2>;
166 hsync-active = <1>;
167 vsync-active = <0>;
168 de-active = <1>;
169 pixelclk-active = <1>;
170 interlaced;
171 doublescan;
172 doubleclk;
173 };
174 timing1: 480x800 {
175 clock-frequency = <9000000>;
176 hactive = <480>;
177 vactive = <800>;
178 hfront-porch = <10>;
179 hback-porch = <59>;
180 hsync-len = <12>;
181 vback-porch = <15>;
182 vfront-porch = <17>;
183 vsync-len = <16>;
184 hsync-active = <0>;
185 vsync-active = <1>;
186 de-active = <0>;
187 pixelclk-active = <0>;
188 };
189 timing2: 800x480 {
190 clock-frequency = <33500000>;
191 hactive = <800>;
192 vactive = <480>;
193 hback-porch = <89>;
194 hfront-porch = <164>;
195 vback-porch = <23>;
196 vfront-porch = <10>;
197 hsync-len = <11>;
198 vsync-len = <13>;
199 };
200 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700201 };
202
203 junk {
Simon Glasscf61f742015-07-06 12:54:36 -0600204 reg = <1 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700205 compatible = "not,compatible";
206 };
207
208 no-compatible {
Simon Glasscf61f742015-07-06 12:54:36 -0600209 reg = <2 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700210 };
211
Simon Glass5620cf82018-10-01 12:22:40 -0600212 backlight: backlight {
213 compatible = "pwm-backlight";
214 enable-gpios = <&gpio_a 1>;
215 power-supply = <&ldo_1>;
216 pwms = <&pwm 0 1000>;
217 default-brightness-level = <5>;
218 brightness-levels = <0 16 32 64 128 170 202 234 255>;
219 };
220
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200221 bind-test {
Patrice Chotard7b7f9392020-07-28 09:13:33 +0200222 compatible = "simple-bus";
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200223 bind-test-child1 {
224 compatible = "sandbox,phy";
225 #phy-cells = <1>;
226 };
227
228 bind-test-child2 {
229 compatible = "simple-bus";
230 };
231 };
232
Simon Glassb2c1cac2014-02-26 15:59:21 -0700233 b-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600234 reg = <3 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700235 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600236 ping-expect = <3>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700237 ping-add = <3>;
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +0530238
239 mux-controls = <&muxcontroller0 0>;
240 mux-control-names = "mux0";
Simon Glassb2c1cac2014-02-26 15:59:21 -0700241 };
242
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200243 phy_provider0: gen_phy@0 {
244 compatible = "sandbox,phy";
245 #phy-cells = <1>;
246 };
247
248 phy_provider1: gen_phy@1 {
249 compatible = "sandbox,phy";
250 #phy-cells = <0>;
251 broken;
252 };
253
developer71092972020-05-02 11:35:12 +0200254 phy_provider2: gen_phy@2 {
255 compatible = "sandbox,phy";
256 #phy-cells = <0>;
257 };
258
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200259 gen_phy_user: gen_phy_user {
260 compatible = "simple-bus";
261 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
262 phy-names = "phy1", "phy2", "phy3";
263 };
264
developer71092972020-05-02 11:35:12 +0200265 gen_phy_user1: gen_phy_user1 {
266 compatible = "simple-bus";
267 phys = <&phy_provider0 0>, <&phy_provider2>;
268 phy-names = "phy1", "phy2";
269 };
270
Simon Glassb2c1cac2014-02-26 15:59:21 -0700271 some-bus {
272 #address-cells = <1>;
273 #size-cells = <0>;
Simon Glass40717422014-07-23 06:55:18 -0600274 compatible = "denx,u-boot-test-bus";
Simon Glasscf61f742015-07-06 12:54:36 -0600275 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600276 ping-expect = <4>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700277 ping-add = <4>;
Simon Glass40717422014-07-23 06:55:18 -0600278 c-test@5 {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700279 compatible = "denx,u-boot-fdt-test";
280 reg = <5>;
Simon Glass40717422014-07-23 06:55:18 -0600281 ping-expect = <5>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700282 ping-add = <5>;
283 };
Simon Glass40717422014-07-23 06:55:18 -0600284 c-test@0 {
285 compatible = "denx,u-boot-fdt-test";
286 reg = <0>;
287 ping-expect = <6>;
288 ping-add = <6>;
289 };
290 c-test@1 {
291 compatible = "denx,u-boot-fdt-test";
292 reg = <1>;
293 ping-expect = <7>;
294 ping-add = <7>;
295 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700296 };
297
298 d-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600299 reg = <3 1>;
Simon Glassdb6f0202014-07-23 06:55:12 -0600300 ping-expect = <6>;
301 ping-add = <6>;
302 compatible = "google,another-fdt-test";
303 };
304
305 e-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600306 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600307 ping-expect = <6>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700308 ping-add = <6>;
309 compatible = "google,another-fdt-test";
310 };
311
Simon Glass0ccb0972015-01-25 08:27:05 -0700312 f-test {
313 compatible = "denx,u-boot-fdt-test";
314 };
315
316 g-test {
317 compatible = "denx,u-boot-fdt-test";
318 };
319
Bin Mengd9d24782018-10-10 22:07:01 -0700320 h-test {
321 compatible = "denx,u-boot-fdt-test1";
322 };
323
developercf8bc132020-05-02 11:35:10 +0200324 i-test {
325 compatible = "mediatek,u-boot-fdt-test";
326 #address-cells = <1>;
327 #size-cells = <0>;
328
329 subnode@0 {
330 reg = <0>;
331 };
332
333 subnode@1 {
334 reg = <1>;
335 };
336
337 subnode@2 {
338 reg = <2>;
339 };
340 };
341
Simon Glass204675c2019-12-29 21:19:25 -0700342 devres-test {
343 compatible = "denx,u-boot-devres-test";
344 };
345
Jean-Jacques Hiblot73873402020-09-11 13:43:35 +0530346 another-test {
347 reg = <0 2>;
348 compatible = "denx,u-boot-fdt-test";
349 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
350 test5-gpios = <&gpio_a 19>;
351 };
352
Nicolas Saenz Julienne22b7f7e2021-01-12 13:55:23 +0100353 mmio-bus@0 {
354 #address-cells = <1>;
355 #size-cells = <1>;
356 compatible = "denx,u-boot-test-bus";
357 dma-ranges = <0x10000000 0x00000000 0x00040000>;
358
359 subnode@0 {
360 compatible = "denx,u-boot-fdt-test";
361 };
362 };
363
364 mmio-bus@1 {
365 #address-cells = <1>;
366 #size-cells = <1>;
367 compatible = "denx,u-boot-test-bus";
Nicolas Saenz Julienne892e9b42021-01-12 13:55:25 +0100368
369 subnode@0 {
370 compatible = "denx,u-boot-fdt-test";
371 };
Nicolas Saenz Julienne22b7f7e2021-01-12 13:55:23 +0100372 };
373
Simon Glass3c601b12020-07-07 13:12:06 -0600374 acpi_test1: acpi-test {
Simon Glass2d67fdf2020-04-08 16:57:34 -0600375 compatible = "denx,u-boot-acpi-test";
Simon Glassd43e0ba2020-07-07 13:12:03 -0600376 acpi-ssdt-test-data = "ab";
Simon Glass990cd5b2020-07-07 13:12:08 -0600377 acpi-dsdt-test-data = "hi";
Simon Glassebb2e832020-07-07 13:11:39 -0600378 child {
379 compatible = "denx,u-boot-acpi-test";
380 };
Simon Glass2d67fdf2020-04-08 16:57:34 -0600381 };
382
Simon Glass3c601b12020-07-07 13:12:06 -0600383 acpi_test2: acpi-test2 {
Simon Glass17968c32020-04-26 09:19:46 -0600384 compatible = "denx,u-boot-acpi-test";
Simon Glassd43e0ba2020-07-07 13:12:03 -0600385 acpi-ssdt-test-data = "cd";
Simon Glass990cd5b2020-07-07 13:12:08 -0600386 acpi-dsdt-test-data = "jk";
Simon Glass17968c32020-04-26 09:19:46 -0600387 };
388
Patrice Chotard9cc2d142017-09-04 14:55:57 +0200389 clocks {
390 clk_fixed: clk-fixed {
391 compatible = "fixed-clock";
392 #clock-cells = <0>;
393 clock-frequency = <1234>;
394 };
Anup Patel8d28c3c2019-02-25 08:14:55 +0000395
396 clk_fixed_factor: clk-fixed-factor {
397 compatible = "fixed-factor-clock";
398 #clock-cells = <0>;
399 clock-div = <3>;
400 clock-mult = <2>;
401 clocks = <&clk_fixed>;
402 };
Lukasz Majewskiccafcdd2019-06-24 15:50:47 +0200403
404 osc {
405 compatible = "fixed-clock";
406 #clock-cells = <0>;
407 clock-frequency = <20000000>;
408 };
Stephen Warrena9622432016-06-17 09:44:00 -0600409 };
410
411 clk_sandbox: clk-sbox {
Simon Glass8cc4d822015-07-06 12:54:24 -0600412 compatible = "sandbox,clk";
Stephen Warrena9622432016-06-17 09:44:00 -0600413 #clock-cells = <1>;
Jean-Jacques Hiblotc1e9c942019-10-22 14:00:07 +0200414 assigned-clocks = <&clk_sandbox 3>;
415 assigned-clock-rates = <321>;
Stephen Warrena9622432016-06-17 09:44:00 -0600416 };
417
418 clk-test {
419 compatible = "sandbox,clk-test";
420 clocks = <&clk_fixed>,
421 <&clk_sandbox 1>,
Jean-Jacques Hiblot98e84182019-10-22 14:00:05 +0200422 <&clk_sandbox 0>,
423 <&clk_sandbox 3>,
424 <&clk_sandbox 2>;
425 clock-names = "fixed", "i2c", "spi", "uart2", "uart1";
Simon Glass8cc4d822015-07-06 12:54:24 -0600426 };
427
Lukasz Majewski8c0709b2019-06-24 15:50:50 +0200428 ccf: clk-ccf {
429 compatible = "sandbox,clk-ccf";
430 };
431
Simon Glass5b968632015-05-22 15:42:15 -0600432 eth@10002000 {
433 compatible = "sandbox,eth";
434 reg = <0x10002000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500435 fake-host-hwaddr = [00 00 66 44 22 00];
Simon Glass5b968632015-05-22 15:42:15 -0600436 };
437
438 eth_5: eth@10003000 {
439 compatible = "sandbox,eth";
440 reg = <0x10003000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500441 fake-host-hwaddr = [00 00 66 44 22 11];
Simon Glass5b968632015-05-22 15:42:15 -0600442 };
443
Bin Meng04a11cb2015-08-27 22:25:53 -0700444 eth_3: sbe5 {
445 compatible = "sandbox,eth";
446 reg = <0x10005000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500447 fake-host-hwaddr = [00 00 66 44 22 33];
Bin Meng04a11cb2015-08-27 22:25:53 -0700448 };
449
Simon Glass5b968632015-05-22 15:42:15 -0600450 eth@10004000 {
451 compatible = "sandbox,eth";
452 reg = <0x10004000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500453 fake-host-hwaddr = [00 00 66 44 22 22];
Simon Glass5b968632015-05-22 15:42:15 -0600454 };
455
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700456 firmware {
457 sandbox_firmware: sandbox-firmware {
458 compatible = "sandbox,firmware";
459 };
Etienne Carriere02fd1262020-09-09 18:44:00 +0200460
461 sandbox-scmi-agent@0 {
462 compatible = "sandbox,scmi-agent";
463 #address-cells = <1>;
464 #size-cells = <0>;
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +0200465
466 clk_scmi0: protocol@14 {
467 reg = <0x14>;
468 #clock-cells = <1>;
469 };
Etienne Carriere8b9b6892020-09-09 18:44:07 +0200470
471 reset_scmi0: protocol@16 {
472 reg = <0x16>;
473 #reset-cells = <1>;
474 };
Etienne Carriere02fd1262020-09-09 18:44:00 +0200475 };
476
477 sandbox-scmi-agent@1 {
478 compatible = "sandbox,scmi-agent";
479 #address-cells = <1>;
480 #size-cells = <0>;
481
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +0200482 clk_scmi1: protocol@14 {
483 reg = <0x14>;
484 #clock-cells = <1>;
485 };
486
Etienne Carriere02fd1262020-09-09 18:44:00 +0200487 protocol@10 {
488 reg = <0x10>;
489 };
490 };
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700491 };
492
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100493 pinctrl-gpio {
494 compatible = "sandbox,pinctrl-gpio";
Simon Glassb2c1cac2014-02-26 15:59:21 -0700495
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100496 gpio_a: base-gpios {
497 compatible = "sandbox,gpio";
498 gpio-controller;
499 #gpio-cells = <1>;
500 gpio-bank-name = "a";
501 sandbox,gpio-count = <20>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200502 hog_input_active_low {
503 gpio-hog;
504 input;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200505 gpios = <10 GPIO_ACTIVE_LOW>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200506 };
507 hog_input_active_high {
508 gpio-hog;
509 input;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200510 gpios = <11 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200511 };
512 hog_output_low {
513 gpio-hog;
514 output-low;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200515 gpios = <12 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200516 };
517 hog_output_high {
518 gpio-hog;
519 output-high;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200520 gpios = <13 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200521 };
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100522 };
523
524 gpio_b: extra-gpios {
525 compatible = "sandbox,gpio";
526 gpio-controller;
527 #gpio-cells = <5>;
528 gpio-bank-name = "b";
529 sandbox,gpio-count = <10>;
530 };
Simon Glass25348a42014-10-13 23:42:11 -0600531
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100532 gpio_c: pinmux-gpios {
533 compatible = "sandbox,gpio";
534 gpio-controller;
535 #gpio-cells = <2>;
536 gpio-bank-name = "c";
537 sandbox,gpio-count = <10>;
538 };
Patrick Delaunay28bdaa52020-01-13 11:35:14 +0100539 };
540
Simon Glass7df766e2014-12-10 08:55:55 -0700541 i2c@0 {
542 #address-cells = <1>;
543 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -0600544 reg = <0 1>;
Simon Glass7df766e2014-12-10 08:55:55 -0700545 compatible = "sandbox,i2c";
546 clock-frequency = <100000>;
547 eeprom@2c {
548 reg = <0x2c>;
549 compatible = "i2c-eeprom";
Simon Glass17b56f62018-11-18 08:14:34 -0700550 sandbox,emul = <&emul_eeprom>;
Michal Simek4f18f922020-05-28 11:48:55 +0200551 partitions {
552 compatible = "fixed-partitions";
553 #address-cells = <1>;
554 #size-cells = <1>;
555 bootcount_i2c: bootcount@10 {
556 reg = <10 2>;
557 };
558 };
Simon Glass7df766e2014-12-10 08:55:55 -0700559 };
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200560
Simon Glass336b2952015-05-22 15:42:17 -0600561 rtc_0: rtc@43 {
562 reg = <0x43>;
563 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700564 sandbox,emul = <&emul0>;
Simon Glass336b2952015-05-22 15:42:17 -0600565 };
566
567 rtc_1: rtc@61 {
568 reg = <0x61>;
569 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700570 sandbox,emul = <&emul1>;
571 };
572
573 i2c_emul: emul {
574 reg = <0xff>;
575 compatible = "sandbox,i2c-emul-parent";
576 emul_eeprom: emul-eeprom {
577 compatible = "sandbox,i2c-eeprom";
578 sandbox,filename = "i2c.bin";
579 sandbox,size = <256>;
580 };
581 emul0: emul0 {
582 compatible = "sandbox,i2c-rtc";
583 };
584 emul1: emull {
Simon Glass336b2952015-05-22 15:42:17 -0600585 compatible = "sandbox,i2c-rtc";
586 };
587 };
588
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200589 sandbox_pmic: sandbox_pmic {
590 reg = <0x40>;
Simon Glass17b56f62018-11-18 08:14:34 -0700591 sandbox,emul = <&emul_pmic0>;
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200592 };
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200593
594 mc34708: pmic@41 {
595 reg = <0x41>;
Simon Glass17b56f62018-11-18 08:14:34 -0700596 sandbox,emul = <&emul_pmic1>;
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200597 };
Simon Glass7df766e2014-12-10 08:55:55 -0700598 };
599
Philipp Tomsich1fc53302018-12-14 21:14:29 +0100600 bootcount@0 {
601 compatible = "u-boot,bootcount-rtc";
602 rtc = <&rtc_1>;
603 offset = <0x13>;
604 };
605
Michal Simek4f18f922020-05-28 11:48:55 +0200606 bootcount {
607 compatible = "u-boot,bootcount-i2c-eeprom";
608 i2c-eeprom = <&bootcount_i2c>;
609 };
610
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100611 adc@0 {
612 compatible = "sandbox,adc";
613 vdd-supply = <&buck2>;
614 vss-microvolts = <0>;
615 };
616
Simon Glass515dcff2020-02-06 09:55:00 -0700617 irq: irq {
Simon Glass54028bc2019-12-06 21:41:59 -0700618 compatible = "sandbox,irq";
Simon Glass515dcff2020-02-06 09:55:00 -0700619 interrupt-controller;
620 #interrupt-cells = <2>;
Simon Glass54028bc2019-12-06 21:41:59 -0700621 };
622
Simon Glass90b6fef2016-01-18 19:52:26 -0700623 lcd {
624 u-boot,dm-pre-reloc;
625 compatible = "sandbox,lcd-sdl";
626 xres = <1366>;
627 yres = <768>;
628 };
629
Simon Glassd783eb32015-07-06 12:54:34 -0600630 leds {
631 compatible = "gpio-leds";
632
633 iracibble {
634 gpios = <&gpio_a 1 0>;
635 label = "sandbox:red";
636 };
637
638 martinet {
639 gpios = <&gpio_a 2 0>;
640 label = "sandbox:green";
641 };
Patrick Bruennb58adfe2018-04-11 11:16:29 +0200642
643 default_on {
644 gpios = <&gpio_a 5 0>;
645 label = "sandbox:default_on";
646 default-state = "on";
647 };
648
649 default_off {
650 gpios = <&gpio_a 6 0>;
Sean Andersonfbf8d652020-09-14 11:02:03 -0400651 /* label intentionally omitted */
Patrick Bruennb58adfe2018-04-11 11:16:29 +0200652 default-state = "off";
653 };
Simon Glassd783eb32015-07-06 12:54:34 -0600654 };
655
Stephen Warren62f2c902016-05-16 17:41:37 -0600656 mbox: mbox {
657 compatible = "sandbox,mbox";
658 #mbox-cells = <1>;
659 };
660
661 mbox-test {
662 compatible = "sandbox,mbox-test";
663 mboxes = <&mbox 100>, <&mbox 1>;
664 mbox-names = "other", "test";
665 };
666
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900667 cpus {
Sean Anderson79d3bba2020-09-28 10:52:23 -0400668 timebase-frequency = <2000000>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900669 cpu-test1 {
Sean Anderson79d3bba2020-09-28 10:52:23 -0400670 timebase-frequency = <3000000>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900671 compatible = "sandbox,cpu_sandbox";
672 u-boot,dm-pre-reloc;
673 };
Mario Sixdea5df72018-08-06 10:23:44 +0200674
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900675 cpu-test2 {
676 compatible = "sandbox,cpu_sandbox";
677 u-boot,dm-pre-reloc;
678 };
Mario Sixdea5df72018-08-06 10:23:44 +0200679
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900680 cpu-test3 {
681 compatible = "sandbox,cpu_sandbox";
682 u-boot,dm-pre-reloc;
683 };
Mario Sixdea5df72018-08-06 10:23:44 +0200684 };
685
Dave Gerlach75dbdfc2020-07-15 23:39:58 -0500686 chipid: chipid {
687 compatible = "sandbox,soc";
688 };
689
Simon Glassc953aaf2018-12-10 10:37:34 -0700690 i2s: i2s {
691 compatible = "sandbox,i2s";
692 #sound-dai-cells = <1>;
Simon Glass4d5814c2019-02-16 20:24:56 -0700693 sandbox,silent; /* Don't emit sounds while testing */
Simon Glassc953aaf2018-12-10 10:37:34 -0700694 };
695
Jean-Jacques Hiblotdb97c7f2019-07-05 09:33:57 +0200696 nop-test_0 {
697 compatible = "sandbox,nop_sandbox1";
698 nop-test_1 {
699 compatible = "sandbox,nop_sandbox2";
700 bind = "True";
701 };
702 nop-test_2 {
703 compatible = "sandbox,nop_sandbox2";
704 bind = "False";
705 };
706 };
707
Mario Sixa8ce0ee2018-07-31 14:24:14 +0200708 misc-test {
709 compatible = "sandbox,misc_sandbox";
710 };
711
Simon Glasse4fef742017-04-23 20:02:07 -0600712 mmc2 {
713 compatible = "sandbox,mmc";
714 };
715
716 mmc1 {
717 compatible = "sandbox,mmc";
718 };
719
720 mmc0 {
Simon Glassd3e58e42015-07-06 12:54:32 -0600721 compatible = "sandbox,mmc";
722 };
723
Simon Glass53a68b32019-02-16 20:24:50 -0700724 pch {
725 compatible = "sandbox,pch";
726 };
727
Tom Rini4a3ca482020-02-11 12:41:23 -0500728 pci0: pci@0 {
Simon Glass3a6eae62015-03-05 12:25:34 -0700729 compatible = "sandbox,pci";
730 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -0500731 bus-range = <0x00 0xff>;
Simon Glass3a6eae62015-03-05 12:25:34 -0700732 #address-cells = <3>;
733 #size-cells = <2>;
Simon Glass35464f72019-09-25 08:56:08 -0600734 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000000
Simon Glass3a6eae62015-03-05 12:25:34 -0700735 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Bin Mengcbf071b2018-08-03 01:14:39 -0700736 pci@0,0 {
737 compatible = "pci-generic";
738 reg = <0x0000 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600739 sandbox,emul = <&swap_case_emul0_0>;
Bin Mengcbf071b2018-08-03 01:14:39 -0700740 };
Alex Margineanf1274432019-06-07 11:24:24 +0300741 pci@1,0 {
742 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -0600743 /* reg 0 is at 0x14, using FDT_PCI_SPACE_MEM32 */
744 reg = <0x02000814 0 0 0 0
745 0x01000810 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600746 sandbox,emul = <&swap_case_emul0_1>;
Alex Margineanf1274432019-06-07 11:24:24 +0300747 };
Simon Glass937bb472019-12-06 21:41:57 -0700748 p2sb-pci@2,0 {
749 compatible = "sandbox,p2sb";
750 reg = <0x02001010 0 0 0 0>;
751 sandbox,emul = <&p2sb_emul>;
752
753 adder {
754 intel,p2sb-port-id = <3>;
755 compatible = "sandbox,adder";
756 };
757 };
Simon Glass8c501022019-12-06 21:41:54 -0700758 pci@1e,0 {
759 compatible = "sandbox,pmc";
760 reg = <0xf000 0 0 0 0>;
761 sandbox,emul = <&pmc_emul1e>;
762 acpi-base = <0x400>;
763 gpe0-dwx-mask = <0xf>;
764 gpe0-dwx-shift-base = <4>;
765 gpe0-dw = <6 7 9>;
766 gpe0-sts = <0x20>;
767 gpe0-en = <0x30>;
768 };
Simon Glass3a6eae62015-03-05 12:25:34 -0700769 pci@1f,0 {
770 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -0600771 /* reg 0 is at 0x10, using FDT_PCI_SPACE_IO */
772 reg = <0x0100f810 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600773 sandbox,emul = <&swap_case_emul0_1f>;
Simon Glass3a6eae62015-03-05 12:25:34 -0700774 };
775 };
776
Simon Glassb98ba4c2019-09-25 08:56:10 -0600777 pci-emul0 {
778 compatible = "sandbox,pci-emul-parent";
779 swap_case_emul0_0: emul0@0,0 {
780 compatible = "sandbox,swap-case";
781 };
782 swap_case_emul0_1: emul0@1,0 {
783 compatible = "sandbox,swap-case";
784 use-ea;
785 };
786 swap_case_emul0_1f: emul0@1f,0 {
787 compatible = "sandbox,swap-case";
788 };
Simon Glass937bb472019-12-06 21:41:57 -0700789 p2sb_emul: emul@2,0 {
790 compatible = "sandbox,p2sb-emul";
791 };
Simon Glass8c501022019-12-06 21:41:54 -0700792 pmc_emul1e: emul@1e,0 {
793 compatible = "sandbox,pmc-emul";
794 };
Simon Glassb98ba4c2019-09-25 08:56:10 -0600795 };
796
Tom Rini4a3ca482020-02-11 12:41:23 -0500797 pci1: pci@1 {
Bin Meng408e5902018-08-03 01:14:41 -0700798 compatible = "sandbox,pci";
799 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -0500800 bus-range = <0x00 0xff>;
Bin Meng408e5902018-08-03 01:14:41 -0700801 #address-cells = <3>;
802 #size-cells = <2>;
Suneel Garapati3ac3aec2019-10-19 17:10:20 -0700803 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000 // MEM0
804 0x02000000 0 0x31000000 0x31000000 0 0x2000 // MEM1
805 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng5fed5362018-08-03 01:14:47 -0700806 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
Marek Vasute5733222018-10-10 21:27:08 +0200807 0x0c 0x00 0x1234 0x5678
808 0x10 0x00 0x1234 0x5678>;
809 pci@10,0 {
810 reg = <0x8000 0 0 0 0>;
811 };
Bin Meng408e5902018-08-03 01:14:41 -0700812 };
813
Tom Rini4a3ca482020-02-11 12:41:23 -0500814 pci2: pci@2 {
Bin Meng510dddb2018-08-03 01:14:50 -0700815 compatible = "sandbox,pci";
816 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -0500817 bus-range = <0x00 0xff>;
Bin Meng510dddb2018-08-03 01:14:50 -0700818 #address-cells = <3>;
819 #size-cells = <2>;
820 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
821 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
822 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
823 pci@1f,0 {
824 compatible = "pci-generic";
825 reg = <0xf800 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600826 sandbox,emul = <&swap_case_emul2_1f>;
827 };
828 };
829
830 pci-emul2 {
831 compatible = "sandbox,pci-emul-parent";
832 swap_case_emul2_1f: emul2@1f,0 {
833 compatible = "sandbox,swap-case";
Bin Meng510dddb2018-08-03 01:14:50 -0700834 };
835 };
836
Ramon Friedc64f19b2019-04-27 11:15:23 +0300837 pci_ep: pci_ep {
838 compatible = "sandbox,pci_ep";
839 };
840
Simon Glass9c433fe2017-04-23 20:10:44 -0600841 probing {
842 compatible = "simple-bus";
843 test1 {
844 compatible = "denx,u-boot-probe-test";
845 };
846
847 test2 {
848 compatible = "denx,u-boot-probe-test";
849 };
850
851 test3 {
852 compatible = "denx,u-boot-probe-test";
853 };
854
855 test4 {
856 compatible = "denx,u-boot-probe-test";
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +0100857 first-syscon = <&syscon0>;
858 second-sys-ctrl = <&another_system_controller>;
Patrick Delaunayee010432019-03-07 09:57:13 +0100859 third-syscon = <&syscon2>;
Simon Glass9c433fe2017-04-23 20:10:44 -0600860 };
861 };
862
Stephen Warren92c67fa2016-07-13 13:45:31 -0600863 pwrdom: power-domain {
864 compatible = "sandbox,power-domain";
865 #power-domain-cells = <1>;
866 };
867
868 power-domain-test {
869 compatible = "sandbox,power-domain-test";
870 power-domains = <&pwrdom 2>;
871 };
872
Simon Glass5620cf82018-10-01 12:22:40 -0600873 pwm: pwm {
Simon Glasse62f4be2017-04-16 21:01:11 -0600874 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -0600875 #pwm-cells = <2>;
Simon Glasse62f4be2017-04-16 21:01:11 -0600876 };
877
878 pwm2 {
879 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -0600880 #pwm-cells = <2>;
Simon Glasse62f4be2017-04-16 21:01:11 -0600881 };
882
Simon Glass3d355e62015-07-06 12:54:31 -0600883 ram {
884 compatible = "sandbox,ram";
885 };
886
Simon Glassd860f222015-07-06 12:54:29 -0600887 reset@0 {
888 compatible = "sandbox,warm-reset";
889 };
890
891 reset@1 {
892 compatible = "sandbox,reset";
893 };
894
Stephen Warren6488e642016-06-17 09:43:59 -0600895 resetc: reset-ctl {
896 compatible = "sandbox,reset-ctl";
897 #reset-cells = <1>;
898 };
899
900 reset-ctl-test {
901 compatible = "sandbox,reset-ctl-test";
902 resets = <&resetc 100>, <&resetc 2>;
903 reset-names = "other", "test";
904 };
905
Sughosh Ganu23e37512019-12-28 23:58:31 +0530906 rng {
907 compatible = "sandbox,sandbox-rng";
908 };
909
Nishanth Menonedf85812015-09-17 15:42:41 -0500910 rproc_1: rproc@1 {
911 compatible = "sandbox,test-processor";
912 remoteproc-name = "remoteproc-test-dev1";
913 };
914
915 rproc_2: rproc@2 {
916 compatible = "sandbox,test-processor";
917 internal-memory-mapped;
918 remoteproc-name = "remoteproc-test-dev2";
919 };
920
Simon Glass5620cf82018-10-01 12:22:40 -0600921 panel {
922 compatible = "simple-panel";
923 backlight = <&backlight 0 100>;
924 };
925
Ramon Fried26ed32e2018-07-02 02:57:59 +0300926 smem@0 {
927 compatible = "sandbox,smem";
928 };
929
Simon Glass76072ac2018-12-10 10:37:36 -0700930 sound {
931 compatible = "sandbox,sound";
932 cpu {
933 sound-dai = <&i2s 0>;
934 };
935
936 codec {
937 sound-dai = <&audio 0>;
938 };
939 };
940
Simon Glass25348a42014-10-13 23:42:11 -0600941 spi@0 {
942 #address-cells = <1>;
943 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -0600944 reg = <0 1>;
Simon Glass25348a42014-10-13 23:42:11 -0600945 compatible = "sandbox,spi";
Ovidiu Panaitae734732020-12-14 19:06:47 +0200946 cs-gpios = <0>, <0>, <&gpio_a 0>;
Simon Glass25348a42014-10-13 23:42:11 -0600947 spi.bin@0 {
948 reg = <0>;
Neil Armstronga009fa72019-02-10 10:16:20 +0000949 compatible = "spansion,m25p16", "jedec,spi-nor";
Simon Glass25348a42014-10-13 23:42:11 -0600950 spi-max-frequency = <40000000>;
951 sandbox,filename = "spi.bin";
952 };
Ovidiu Panaitae734732020-12-14 19:06:47 +0200953 spi.bin@1 {
954 reg = <1>;
955 compatible = "spansion,m25p16", "jedec,spi-nor";
956 spi-max-frequency = <50000000>;
957 sandbox,filename = "spi.bin";
958 spi-cpol;
959 spi-cpha;
960 };
Simon Glass25348a42014-10-13 23:42:11 -0600961 };
962
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +0100963 syscon0: syscon@0 {
Simon Glasscd556522015-07-06 12:54:35 -0600964 compatible = "sandbox,syscon0";
Mario Sixe3f59f42018-10-04 09:00:40 +0200965 reg = <0x10 16>;
Simon Glasscd556522015-07-06 12:54:35 -0600966 };
967
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +0100968 another_system_controller: syscon@1 {
Simon Glasscd556522015-07-06 12:54:35 -0600969 compatible = "sandbox,syscon1";
Simon Glasscf61f742015-07-06 12:54:36 -0600970 reg = <0x20 5
971 0x28 6
972 0x30 7
973 0x38 8>;
Simon Glasscd556522015-07-06 12:54:35 -0600974 };
975
Patrick Delaunayee010432019-03-07 09:57:13 +0100976 syscon2: syscon@2 {
Masahiro Yamada42ab1072018-04-23 13:26:53 +0900977 compatible = "simple-mfd", "syscon";
978 reg = <0x40 5
979 0x48 6
980 0x50 7
981 0x58 8>;
982 };
983
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +0530984 syscon3: syscon@3 {
985 compatible = "simple-mfd", "syscon";
986 reg = <0x000100 0x10>;
987
988 muxcontroller0: a-mux-controller {
989 compatible = "mmio-mux";
990 #mux-control-cells = <1>;
991
992 mux-reg-masks = <0x0 0x30>, /* 0: reg 0x0, bits 5:4 */
993 <0xc 0x1E>, /* 1: reg 0xc, bits 4:1 */
994 <0x4 0xFF>; /* 2: reg 0x4, bits 7:0 */
995 idle-states = <MUX_IDLE_AS_IS>, <0x02>, <0x73>;
996 u-boot,mux-autoprobe;
997 };
998 };
999
1000 muxcontroller1: emul-mux-controller {
1001 compatible = "mux-emul";
1002 #mux-control-cells = <0>;
1003 u-boot,mux-autoprobe;
1004 idle-state = <0xabcd>;
1005 };
1006
Simon Glass791a17f2020-12-16 21:20:27 -07001007 testfdtm0 {
1008 compatible = "denx,u-boot-fdtm-test";
1009 };
1010
1011 testfdtm1: testfdtm1 {
1012 compatible = "denx,u-boot-fdtm-test";
1013 };
1014
1015 testfdtm2 {
1016 compatible = "denx,u-boot-fdtm-test";
1017 };
1018
Sean Anderson79d3bba2020-09-28 10:52:23 -04001019 timer@0 {
Thomas Chou6f2cfbf2015-12-11 16:27:34 +08001020 compatible = "sandbox,timer";
1021 clock-frequency = <1000000>;
1022 };
1023
Sean Anderson79d3bba2020-09-28 10:52:23 -04001024 timer@1 {
1025 compatible = "sandbox,timer";
1026 sandbox,timebase-frequency-fallback;
1027 };
1028
Miquel Raynal80938c12018-05-15 11:57:27 +02001029 tpm2 {
1030 compatible = "sandbox,tpm2";
1031 };
1032
Simon Glass5b968632015-05-22 15:42:15 -06001033 uart0: serial {
1034 compatible = "sandbox,serial";
1035 u-boot,dm-pre-reloc;
Joe Hershberger4c197242015-03-22 17:09:15 -05001036 };
1037
Simon Glass31680482015-03-25 12:23:05 -06001038 usb_0: usb@0 {
1039 compatible = "sandbox,usb";
1040 status = "disabled";
1041 hub {
1042 compatible = "sandbox,usb-hub";
1043 #address-cells = <1>;
1044 #size-cells = <0>;
1045 flash-stick {
1046 reg = <0>;
1047 compatible = "sandbox,usb-flash";
1048 };
1049 };
1050 };
1051
1052 usb_1: usb@1 {
1053 compatible = "sandbox,usb";
1054 hub {
1055 compatible = "usb-hub";
1056 usb,device-class = <9>;
Michael Walle7c961322020-06-02 01:47:07 +02001057 #address-cells = <1>;
1058 #size-cells = <0>;
Simon Glass31680482015-03-25 12:23:05 -06001059 hub-emul {
1060 compatible = "sandbox,usb-hub";
1061 #address-cells = <1>;
1062 #size-cells = <0>;
Simon Glass4700fe52015-11-08 23:48:01 -07001063 flash-stick@0 {
Simon Glass31680482015-03-25 12:23:05 -06001064 reg = <0>;
1065 compatible = "sandbox,usb-flash";
1066 sandbox,filepath = "testflash.bin";
1067 };
1068
Simon Glass4700fe52015-11-08 23:48:01 -07001069 flash-stick@1 {
1070 reg = <1>;
1071 compatible = "sandbox,usb-flash";
1072 sandbox,filepath = "testflash1.bin";
1073 };
1074
1075 flash-stick@2 {
1076 reg = <2>;
1077 compatible = "sandbox,usb-flash";
1078 sandbox,filepath = "testflash2.bin";
1079 };
1080
Simon Glassc0ccc722015-11-08 23:48:08 -07001081 keyb@3 {
1082 reg = <3>;
1083 compatible = "sandbox,usb-keyb";
1084 };
1085
Simon Glass31680482015-03-25 12:23:05 -06001086 };
Michael Walle7c961322020-06-02 01:47:07 +02001087
1088 usbstor@1 {
1089 reg = <1>;
1090 };
1091 usbstor@3 {
1092 reg = <3>;
1093 };
Simon Glass31680482015-03-25 12:23:05 -06001094 };
1095 };
1096
1097 usb_2: usb@2 {
1098 compatible = "sandbox,usb";
1099 status = "disabled";
1100 };
1101
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001102 spmi: spmi@0 {
1103 compatible = "sandbox,spmi";
1104 #address-cells = <0x1>;
1105 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -06001106 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001107 pm8916@0 {
1108 compatible = "qcom,spmi-pmic";
1109 reg = <0x0 0x1>;
1110 #address-cells = <0x1>;
1111 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -06001112 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001113
1114 spmi_gpios: gpios@c000 {
1115 compatible = "qcom,pm8916-gpio";
1116 reg = <0xc000 0x400>;
1117 gpio-controller;
1118 gpio-count = <4>;
1119 #gpio-cells = <2>;
1120 gpio-bank-name="spmi";
1121 };
1122 };
1123 };
maxims@google.comdaea6d42017-04-17 12:00:21 -07001124
1125 wdt0: wdt@0 {
1126 compatible = "sandbox,wdt";
1127 };
Rob Clarka471b672018-01-10 11:33:30 +01001128
Mario Six95922152018-08-09 14:51:19 +02001129 axi: axi@0 {
1130 compatible = "sandbox,axi";
1131 #address-cells = <0x1>;
1132 #size-cells = <0x1>;
1133 store@0 {
1134 compatible = "sandbox,sandbox_store";
1135 reg = <0x0 0x400>;
1136 };
1137 };
1138
Rob Clarka471b672018-01-10 11:33:30 +01001139 chosen {
Simon Glass305ac9a2018-02-03 10:36:58 -07001140 #address-cells = <1>;
1141 #size-cells = <1>;
Simon Glassf3455962020-01-27 08:49:43 -07001142 setting = "sunrise ohoka";
1143 other-node = "/some-bus/c-test@5";
Simon Glasse09223c2020-01-27 08:49:46 -07001144 int-values = <0x1937 72993>;
Simon Glass3c601b12020-07-07 13:12:06 -06001145 u-boot,acpi-ssdt-order = <&acpi_test2 &acpi_test1>;
Rob Clarka471b672018-01-10 11:33:30 +01001146 chosen-test {
1147 compatible = "denx,u-boot-fdt-test";
1148 reg = <9 1>;
1149 };
1150 };
Mario Six35616ef2018-03-12 14:53:33 +01001151
1152 translation-test@8000 {
1153 compatible = "simple-bus";
1154 reg = <0x8000 0x4000>;
1155
1156 #address-cells = <0x2>;
1157 #size-cells = <0x1>;
1158
1159 ranges = <0 0x0 0x8000 0x1000
1160 1 0x100 0x9000 0x1000
1161 2 0x200 0xA000 0x1000
1162 3 0x300 0xB000 0x1000
Dario Binacchib574d682020-12-30 00:16:21 +01001163 4 0x400 0xC000 0x1000
Mario Six35616ef2018-03-12 14:53:33 +01001164 >;
1165
Fabien Dessenne22236e02019-05-31 15:11:30 +02001166 dma-ranges = <0 0x000 0x10000000 0x1000
1167 1 0x100 0x20000000 0x1000
1168 >;
1169
Mario Six35616ef2018-03-12 14:53:33 +01001170 dev@0,0 {
1171 compatible = "denx,u-boot-fdt-dummy";
1172 reg = <0 0x0 0x1000>;
Álvaro Fernández Rojasa3181152018-12-03 19:37:09 +01001173 reg-names = "sandbox-dummy-0";
Mario Six35616ef2018-03-12 14:53:33 +01001174 };
1175
1176 dev@1,100 {
1177 compatible = "denx,u-boot-fdt-dummy";
1178 reg = <1 0x100 0x1000>;
1179
1180 };
1181
1182 dev@2,200 {
1183 compatible = "denx,u-boot-fdt-dummy";
1184 reg = <2 0x200 0x1000>;
1185 };
1186
1187
1188 noxlatebus@3,300 {
1189 compatible = "simple-bus";
1190 reg = <3 0x300 0x1000>;
1191
1192 #address-cells = <0x1>;
1193 #size-cells = <0x0>;
1194
1195 dev@42 {
1196 compatible = "denx,u-boot-fdt-dummy";
1197 reg = <0x42>;
1198 };
1199 };
Dario Binacchib574d682020-12-30 00:16:21 +01001200
1201 xlatebus@4,400 {
1202 compatible = "sandbox,zero-size-cells-bus";
1203 reg = <4 0x400 0x1000>;
1204 #address-cells = <1>;
1205 #size-cells = <1>;
1206 ranges = <0 4 0x400 0x1000>;
1207
1208 devs {
1209 #address-cells = <1>;
1210 #size-cells = <0>;
1211
1212 dev@19 {
1213 compatible = "denx,u-boot-fdt-dummy";
1214 reg = <0x19>;
1215 };
1216 };
1217 };
1218
Mario Six35616ef2018-03-12 14:53:33 +01001219 };
Mario Six02ad6fb2018-09-27 09:19:31 +02001220
1221 osd {
1222 compatible = "sandbox,sandbox_osd";
1223 };
Tom Rinib93eea72018-09-30 18:16:51 -04001224
Jens Wiklander86afaa62018-09-25 16:40:16 +02001225 sandbox_tee {
1226 compatible = "sandbox,tee";
1227 };
Bin Meng1bb290d2018-10-15 02:21:26 -07001228
1229 sandbox_virtio1 {
1230 compatible = "sandbox,virtio1";
1231 };
1232
1233 sandbox_virtio2 {
1234 compatible = "sandbox,virtio2";
1235 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001236
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +02001237 sandbox_scmi {
1238 compatible = "sandbox,scmi-devices";
1239 clocks = <&clk_scmi0 7>, <&clk_scmi0 3>, <&clk_scmi1 1>;
Etienne Carriere8b9b6892020-09-09 18:44:07 +02001240 resets = <&reset_scmi0 3>;
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +02001241 };
1242
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001243 pinctrl {
1244 compatible = "sandbox,pinctrl";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001245
Sean Anderson3438e3b2020-09-14 11:01:57 -04001246 pinctrl-names = "default", "alternate";
1247 pinctrl-0 = <&pinctrl_gpios>, <&pinctrl_i2s>;
1248 pinctrl-1 = <&pinctrl_spi>, <&pinctrl_i2c>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001249
Sean Anderson3438e3b2020-09-14 11:01:57 -04001250 pinctrl_gpios: gpios {
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001251 gpio0 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001252 pins = "P5";
1253 function = "GPIO";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001254 bias-pull-up;
1255 input-disable;
1256 };
1257 gpio1 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001258 pins = "P6";
1259 function = "GPIO";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001260 output-high;
1261 drive-open-drain;
1262 };
1263 gpio2 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001264 pinmux = <SANDBOX_PINMUX(7, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001265 bias-pull-down;
1266 input-enable;
1267 };
1268 gpio3 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001269 pinmux = <SANDBOX_PINMUX(8, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001270 bias-disable;
1271 };
1272 };
Sean Anderson3438e3b2020-09-14 11:01:57 -04001273
1274 pinctrl_i2c: i2c {
1275 groups {
1276 groups = "I2C_UART";
1277 function = "I2C";
1278 };
1279
1280 pins {
1281 pins = "P0", "P1";
1282 drive-open-drain;
1283 };
1284 };
1285
1286 pinctrl_i2s: i2s {
1287 groups = "SPI_I2S";
1288 function = "I2S";
1289 };
1290
1291 pinctrl_spi: spi {
1292 groups = "SPI_I2S";
1293 function = "SPI";
1294
1295 cs {
1296 pinmux = <SANDBOX_PINMUX(5, SANDBOX_PINMUX_CS)>,
1297 <SANDBOX_PINMUX(6, SANDBOX_PINMUX_CS)>;
1298 };
1299 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001300 };
Benjamin Gaignarda550b542018-11-27 13:49:50 +01001301
1302 hwspinlock@0 {
1303 compatible = "sandbox,hwspinlock";
1304 };
Grygorii Strashko19ebf0b2018-11-28 19:17:51 +01001305
1306 dma: dma {
1307 compatible = "sandbox,dma";
1308 #dma-cells = <1>;
1309
1310 dmas = <&dma 0>, <&dma 1>, <&dma 2>;
1311 dma-names = "m2m", "tx0", "rx0";
1312 };
Alex Marginean0daa53a2019-06-03 19:12:28 +03001313
Alex Marginean0649be52019-07-12 10:13:53 +03001314 /*
1315 * keep mdio-mux ahead of mdio so that the mux is removed first at the
1316 * end of the test. If parent mdio is removed first, clean-up of the
1317 * mux will trigger a 2nd probe of parent-mdio, leaving parent-mdio
1318 * active at the end of the test. That it turn doesn't allow the mdio
1319 * class to be destroyed, triggering an error.
1320 */
1321 mdio-mux-test {
1322 compatible = "sandbox,mdio-mux";
1323 #address-cells = <1>;
1324 #size-cells = <0>;
1325 mdio-parent-bus = <&mdio>;
1326
1327 mdio-ch-test@0 {
1328 reg = <0>;
1329 };
1330 mdio-ch-test@1 {
1331 reg = <1>;
1332 };
1333 };
1334
1335 mdio: mdio-test {
Alex Marginean0daa53a2019-06-03 19:12:28 +03001336 compatible = "sandbox,mdio";
1337 };
Sean Andersonb7860542020-06-24 06:41:12 -04001338
1339 pm-bus-test {
1340 compatible = "simple-pm-bus";
1341 clocks = <&clk_sandbox 4>;
1342 power-domains = <&pwrdom 1>;
1343 };
Sean Anderson0c1f6bf2020-06-24 06:41:14 -04001344
1345 resetc2: syscon-reset {
1346 compatible = "syscon-reset";
1347 #reset-cells = <1>;
1348 regmap = <&syscon0>;
1349 offset = <1>;
1350 mask = <0x27FFFFFF>;
1351 assert-high = <0>;
1352 };
1353
1354 syscon-reset-test {
1355 compatible = "sandbox,misc_sandbox";
1356 resets = <&resetc2 15>, <&resetc2 30>, <&resetc2 60>;
1357 reset-names = "valid", "no_mask", "out_of_range";
1358 };
Jean-Jacques Hiblot0b89fc52020-09-24 10:04:18 +05301359
Simon Glass458b66a2020-11-05 06:32:05 -07001360 sysinfo {
1361 compatible = "sandbox,sysinfo-sandbox";
1362 };
1363
Jean-Jacques Hiblot0b89fc52020-09-24 10:04:18 +05301364 some_regmapped-bus {
1365 #address-cells = <0x1>;
1366 #size-cells = <0x1>;
1367
1368 ranges = <0x0 0x0 0x10>;
1369 compatible = "simple-bus";
1370
1371 regmap-test_0 {
1372 reg = <0 0x10>;
1373 compatible = "sandbox,regmap_test";
1374 };
1375 };
Simon Glassb2c1cac2014-02-26 15:59:21 -07001376};
Przemyslaw Marczak77bee052015-05-13 13:38:35 +02001377
1378#include "sandbox_pmic.dtsi"