Stefan Roese | 65da15e | 2018-09-05 15:12:35 +0200 | [diff] [blame] | 1 | menu "MediaTek MIPS platforms" |
developer | 89f051b | 2019-04-30 11:13:58 +0800 | [diff] [blame] | 2 | depends on ARCH_MTMIPS |
Stefan Roese | 65da15e | 2018-09-05 15:12:35 +0200 | [diff] [blame] | 3 | |
| 4 | config SYS_MALLOC_F_LEN |
| 5 | default 0x1000 |
| 6 | |
| 7 | config SYS_SOC |
developer | 89f051b | 2019-04-30 11:13:58 +0800 | [diff] [blame] | 8 | default "mt7628" if SOC_MT7628 |
Stefan Roese | 65da15e | 2018-09-05 15:12:35 +0200 | [diff] [blame] | 9 | |
developer | 26f763e | 2020-04-21 09:28:26 +0200 | [diff] [blame] | 10 | config SYS_DCACHE_SIZE |
| 11 | default 32768 |
| 12 | |
| 13 | config SYS_DCACHE_LINE_SIZE |
| 14 | default 32 |
| 15 | |
| 16 | config SYS_ICACHE_SIZE |
| 17 | default 65536 |
| 18 | |
| 19 | config SYS_ICACHE_LINE_SIZE |
| 20 | default 32 |
| 21 | |
Stefan Roese | 65da15e | 2018-09-05 15:12:35 +0200 | [diff] [blame] | 22 | choice |
| 23 | prompt "MediaTek MIPS SoC select" |
| 24 | |
developer | 89f051b | 2019-04-30 11:13:58 +0800 | [diff] [blame] | 25 | config SOC_MT7628 |
| 26 | bool "MT7628" |
Stefan Roese | 65da15e | 2018-09-05 15:12:35 +0200 | [diff] [blame] | 27 | select MIPS_L1_CACHE_SHIFT_5 |
developer | 591826e | 2019-09-25 17:45:43 +0800 | [diff] [blame] | 28 | select PINCTRL_MT7628 |
| 29 | select MTK_SERIAL |
Stefan Roese | 65da15e | 2018-09-05 15:12:35 +0200 | [diff] [blame] | 30 | help |
developer | 89f051b | 2019-04-30 11:13:58 +0800 | [diff] [blame] | 31 | This supports MediaTek MT7628/MT7688. |
Stefan Roese | 65da15e | 2018-09-05 15:12:35 +0200 | [diff] [blame] | 32 | |
| 33 | endchoice |
| 34 | |
| 35 | choice |
| 36 | prompt "Board select" |
| 37 | |
Stefan Roese | 115802d | 2018-08-16 15:27:31 +0200 | [diff] [blame] | 38 | config BOARD_GARDENA_SMART_GATEWAY_MT7688 |
Stefan Roese | f08cc08 | 2019-03-15 09:09:34 +0100 | [diff] [blame] | 39 | bool "GARDENA smart Gateway" |
developer | 89f051b | 2019-04-30 11:13:58 +0800 | [diff] [blame] | 40 | depends on SOC_MT7628 |
Stefan Roese | d0fdd67 | 2018-10-09 08:59:13 +0200 | [diff] [blame] | 41 | select BOARD_LATE_INIT |
Stefan Roese | 115802d | 2018-08-16 15:27:31 +0200 | [diff] [blame] | 42 | select SUPPORTS_BOOT_RAM |
| 43 | help |
Stefan Roese | f08cc08 | 2019-03-15 09:09:34 +0100 | [diff] [blame] | 44 | GARDENA smart Gateway boards have a MT7688 SoC with 128 MiB of RAM |
Stefan Roese | 115802d | 2018-08-16 15:27:31 +0200 | [diff] [blame] | 45 | and 8 MiB of flash (SPI NOR) and additional SPI NAND storage. |
| 46 | |
Stefan Roese | 2052a93 | 2018-08-16 15:27:30 +0200 | [diff] [blame] | 47 | config BOARD_LINKIT_SMART_7688 |
| 48 | bool "LinkIt Smart 7688" |
developer | 89f051b | 2019-04-30 11:13:58 +0800 | [diff] [blame] | 49 | depends on SOC_MT7628 |
Stefan Roese | 2052a93 | 2018-08-16 15:27:30 +0200 | [diff] [blame] | 50 | select SUPPORTS_BOOT_RAM |
| 51 | help |
| 52 | Seeed LinkIt Smart 7688 boards have a MT7688 SoC with 128 MiB of RAM |
| 53 | and 32 MiB of flash (SPI). |
| 54 | Between its different peripherals there's an integrated switch with 4 |
| 55 | ethernet ports, 1 USB port, 1 UART, GPIO buttons and LEDs, and |
| 56 | a MT7688 (PCIe). |
| 57 | |
Stefan Roese | 65da15e | 2018-09-05 15:12:35 +0200 | [diff] [blame] | 58 | endchoice |
| 59 | |
| 60 | choice |
| 61 | prompt "Boot mode" |
| 62 | |
| 63 | config BOOT_RAM |
| 64 | bool "RAM boot" |
| 65 | depends on SUPPORTS_BOOT_RAM |
| 66 | help |
| 67 | This builds an image that is linked to a RAM address. It can be used |
| 68 | for booting from CFE via TFTP using an ELF image, but it can also be |
| 69 | booted from RAM by other bootloaders using a BIN image. |
| 70 | |
| 71 | config BOOT_ROM |
| 72 | bool "ROM boot" |
| 73 | depends on SUPPORTS_BOOT_RAM |
| 74 | help |
| 75 | This builds an image that is linked to a ROM address. It can be |
| 76 | used as main bootloader image which is programmed onto the onboard |
| 77 | flash storage (SPI NOR). |
| 78 | |
| 79 | endchoice |
| 80 | |
| 81 | choice |
| 82 | prompt "DDR2 size" |
| 83 | |
| 84 | config ONBOARD_DDR2_SIZE_256MBIT |
| 85 | bool "256MBit (32MByte) total size" |
| 86 | depends on BOOT_ROM |
| 87 | help |
| 88 | Use 256MBit (32MByte) of DDR total size |
| 89 | |
| 90 | config ONBOARD_DDR2_SIZE_512MBIT |
| 91 | bool "512MBit (64MByte) total size" |
| 92 | depends on BOOT_ROM |
| 93 | help |
| 94 | Use 512MBit (64MByte) of DDR total size |
| 95 | |
| 96 | config ONBOARD_DDR2_SIZE_1024MBIT |
| 97 | bool "1024MBit (128MByte) total size" |
| 98 | depends on BOOT_ROM |
| 99 | help |
| 100 | Use 1024MBit (128MByte) of DDR total size |
| 101 | |
| 102 | config ONBOARD_DDR2_SIZE_2048MBIT |
| 103 | bool "2048MBit (256MByte) total size" |
| 104 | depends on BOOT_ROM |
| 105 | help |
| 106 | Use 2048MBit (256MByte) of DDR total size |
| 107 | |
| 108 | endchoice |
| 109 | |
| 110 | choice |
| 111 | prompt "DDR2 chip width" |
| 112 | |
| 113 | config ONBOARD_DDR2_CHIP_WIDTH_8BIT |
| 114 | bool "8bit DDR chip width" |
| 115 | depends on BOOT_ROM |
| 116 | help |
| 117 | Use DDR chips with 8bit width |
| 118 | |
| 119 | config ONBOARD_DDR2_CHIP_WIDTH_16BIT |
| 120 | bool "16bit DDR chip width" |
| 121 | depends on BOOT_ROM |
| 122 | help |
| 123 | Use DDR chips with 16bit width |
| 124 | |
| 125 | endchoice |
| 126 | |
| 127 | choice |
| 128 | prompt "DDR2 bus width" |
| 129 | |
| 130 | config ONBOARD_DDR2_BUS_WIDTH_16BIT |
| 131 | bool "16bit DDR bus width" |
| 132 | depends on BOOT_ROM |
| 133 | help |
| 134 | Use 16bit DDR bus width |
| 135 | |
| 136 | config ONBOARD_DDR2_BUS_WIDTH_32BIT |
| 137 | bool "32bit DDR bus width" |
| 138 | depends on BOOT_ROM |
| 139 | help |
| 140 | Use 32bit DDR bus width |
| 141 | |
| 142 | endchoice |
| 143 | |
| 144 | config SUPPORTS_BOOT_RAM |
| 145 | bool |
| 146 | |
Stefan Roese | 115802d | 2018-08-16 15:27:31 +0200 | [diff] [blame] | 147 | source "board/gardena/smart-gateway-mt7688/Kconfig" |
Stefan Roese | 2052a93 | 2018-08-16 15:27:30 +0200 | [diff] [blame] | 148 | source "board/seeed/linkit-smart-7688/Kconfig" |
| 149 | |
Stefan Roese | 65da15e | 2018-09-05 15:12:35 +0200 | [diff] [blame] | 150 | endmenu |