| Wolfgang Denk | 4dc1146 | 2005-09-26 01:06:33 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Initialization stuff - taken from hermit |
| 3 | * (C) Copyright 2005 Rowel Atienza <rowel@diwalabs.com> |
| 4 | * Armadillo board HT1070 |
| 5 | * |
| 6 | * See file CREDITS for list of people who contributed to this |
| 7 | * project. |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or |
| 10 | * modify it under the terms of the GNU General Public License as |
| 11 | * published by the Free Software Foundation; either version 2 of |
| 12 | * the License, or (at your option) any later version. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 22 | * MA 02111-1307 USA |
| 23 | */ |
| 24 | |
| 25 | |
| 26 | #include <config.h> |
| 27 | #include <version.h> |
| 28 | |
| 29 | |
| 30 | /* some parameters for the board */ |
| 31 | /* setting up the memory */ |
| 32 | #define SRAM_START 0x60000000 |
| 33 | #define SRAM_SIZE 0x0000c000 |
| 34 | |
| 35 | .globl lowlevel_init |
| 36 | lowlevel_init: |
| 37 | mov r0, #0x70 /* 32-bit code + data, MMU mandatory */ |
| 38 | mcr p15, 0, r0, c1, c0, 0 /* MMU init */ |
| 39 | |
| 40 | mov r0, #0 |
| 41 | mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ |
| 42 | mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ |
| 43 | |
| 44 | mov r0, #0x80000000 /* I/O base */ |
| 45 | |
| 46 | mov r1, #0x6 /* CLKCTL_73 in SYSCON3 */ |
| 47 | add r2, r0, #0x2200 /* address of SYSCON3 in r2 */ |
| 48 | str r1, [r2] /* set clock speed to 73.728 MHz */ |
| 49 | |
| 50 | mov r1, #0x81 /* 64KHz DRAM refresh period */ |
| 51 | str r1, [r0, #0x200] /* set DRFPR */ |
| 52 | |
| 53 | mov r1, #0x500 /* permanent enable, 16bits wide */ |
| 54 | add r1, r1, #0x42 /* 128Mbit, CAS lat = 2 SDRAM */ |
| 55 | add r2, r0, #0x2300 /* load address in r2 */ |
| 56 | str r1, [r2] |
| 57 | |
| 58 | mov r1, #0x100 /* SDRAM refresh rate */ |
| 59 | add r2, r0, #0x2340 /* load address in r2 */ |
| 60 | str r1, [r2] |
| 61 | |
| 62 | mov sp, #SRAM_START /* init stack pointer */ |
| 63 | add sp, sp, #SRAM_SIZE |
| 64 | |
| 65 | /* everything is fine now */ |
| 66 | mov pc, lr |