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Tom Warren41b68382011-01-27 10:58:05 +00001/*
2 * (C) Copyright 2010,2011
3 * NVIDIA Corporation <www.nvidia.com>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <ns16550.h>
26#include <asm/io.h>
27#include <asm/arch/tegra2.h>
28#include <asm/arch/sys_proto.h>
29
30#include <asm/arch/clk_rst.h>
Simon Glass16134fd2011-08-30 06:23:13 +000031#include <asm/arch/clock.h>
Tom Warren41b68382011-01-27 10:58:05 +000032#include <asm/arch/pinmux.h>
33#include <asm/arch/uart.h>
Tom Warren112a1882011-04-14 12:18:06 +000034#include "board.h"
Tom Warren41b68382011-01-27 10:58:05 +000035
36DECLARE_GLOBAL_DATA_PTR;
37
38const struct tegra2_sysinfo sysinfo = {
39 CONFIG_TEGRA2_BOARD_STRING
40};
41
42/*
43 * Routine: timer_init
44 * Description: init the timestamp and lastinc value
45 */
46int timer_init(void)
47{
Tom Warren41b68382011-01-27 10:58:05 +000048 return 0;
49}
50
Simon Glassc2ea5e42011-09-21 12:40:04 +000051static void enable_uart(enum periph_id pid)
Tom Warren41b68382011-01-27 10:58:05 +000052{
Simon Glass16134fd2011-08-30 06:23:13 +000053 /* Assert UART reset and enable clock */
Simon Glassc2ea5e42011-09-21 12:40:04 +000054 reset_set_enable(pid, 1);
55 clock_enable(pid);
56 clock_ll_set_source(pid, 0); /* UARTx_CLK_SRC = 00, PLLP_OUT0 */
Tom Warren41b68382011-01-27 10:58:05 +000057
58 /* wait for 2us */
59 udelay(2);
60
61 /* De-assert reset to UART */
Simon Glassc2ea5e42011-09-21 12:40:04 +000062 reset_set_enable(pid, 0);
63}
64
65/*
66 * Routine: clock_init_uart
67 * Description: init the PLL and clock for the UART(s)
68 */
69static void clock_init_uart(void)
70{
71#if defined(CONFIG_TEGRA2_ENABLE_UARTA)
72 enable_uart(PERIPH_ID_UART1);
Tom Warren41b68382011-01-27 10:58:05 +000073#endif /* CONFIG_TEGRA2_ENABLE_UARTA */
74#if defined(CONFIG_TEGRA2_ENABLE_UARTD)
Simon Glassc2ea5e42011-09-21 12:40:04 +000075 enable_uart(PERIPH_ID_UART4);
Tom Warren41b68382011-01-27 10:58:05 +000076#endif /* CONFIG_TEGRA2_ENABLE_UARTD */
77}
78
79/*
80 * Routine: pin_mux_uart
81 * Description: setup the pin muxes/tristate values for the UART(s)
82 */
83static void pin_mux_uart(void)
84{
Tom Warren41b68382011-01-27 10:58:05 +000085#if defined(CONFIG_TEGRA2_ENABLE_UARTA)
Simon Glassb70bbf12011-09-21 12:40:06 +000086 pinmux_set_func(PINGRP_IRRX, PMUX_FUNC_UARTA);
87 pinmux_set_func(PINGRP_IRTX, PMUX_FUNC_UARTA);
Tom Warren41b68382011-01-27 10:58:05 +000088
Simon Glass80608ed2011-09-21 12:40:05 +000089 pinmux_tristate_disable(PINGRP_IRRX);
90 pinmux_tristate_disable(PINGRP_IRTX);
Tom Warren41b68382011-01-27 10:58:05 +000091#endif /* CONFIG_TEGRA2_ENABLE_UARTA */
92#if defined(CONFIG_TEGRA2_ENABLE_UARTD)
Simon Glassb70bbf12011-09-21 12:40:06 +000093 pinmux_set_func(PINGRP_GMC, PMUX_FUNC_UARTD);
Tom Warren41b68382011-01-27 10:58:05 +000094
Simon Glass80608ed2011-09-21 12:40:05 +000095 pinmux_tristate_disable(PINGRP_GMC);
Tom Warren41b68382011-01-27 10:58:05 +000096#endif /* CONFIG_TEGRA2_ENABLE_UARTD */
97}
Tom Warrene1495582011-04-14 12:09:41 +000098
99/*
Tom Warren41b68382011-01-27 10:58:05 +0000100 * Routine: board_init
101 * Description: Early hardware init.
102 */
103int board_init(void)
104{
Simon Glassc2ea5e42011-09-21 12:40:04 +0000105 clock_init();
106 clock_verify();
107
Tom Warren41b68382011-01-27 10:58:05 +0000108 /* boot param addr */
109 gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100);
Tom Warren41b68382011-01-27 10:58:05 +0000110
Tom Warren41b68382011-01-27 10:58:05 +0000111 return 0;
112}
Simon Glassdfcee792011-09-21 12:40:03 +0000113
114#ifdef CONFIG_BOARD_EARLY_INIT_F
115int board_early_init_f(void)
116{
Simon Glass71032212011-11-05 03:56:52 +0000117 /* We didn't do this init in start.S, so do it now */
118 cpu_init_cp15();
119
Simon Glassc2ea5e42011-09-21 12:40:04 +0000120 /* Initialize essential common plls */
121 clock_early_init();
122
Simon Glassdfcee792011-09-21 12:40:03 +0000123 /* Initialize UART clocks */
124 clock_init_uart();
125
126 /* Initialize periph pinmuxes */
127 pin_mux_uart();
128
129 /* Initialize periph GPIOs */
130 gpio_config_uart();
Simon Glassdfcee792011-09-21 12:40:03 +0000131 return 0;
132}
133#endif /* EARLY_INIT */