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git01.mediatek.com / filogic / uboot / 3ae0f50e4e2a457fc1d0c1d361c1a58181419339 / . / include / configs / mt7620.h
blob: d5bd492634844fa419c068e90763769d203eff25 [file] [log] [blame]
developer18ec8d62020-11-12 16:35:52 +0800[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2020 MediaTek Inc. All Rights Reserved.
4 *
5 * Author: Weijie Gao <weijie.gao@mediatek.com>
6 */
7
8#ifndef __CONFIG_MT7620_H
9#define __CONFIG_MT7620_H
10
Tom Rinibb4dd962022-11-16 13:10:37 -0500[diff] [blame]11#define CFG_SYS_SDRAM_BASE 0x80000000
developer18ec8d62020-11-12 16:35:52 +0800[diff] [blame]12
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]13#define CFG_SYS_INIT_SP_OFFSET 0x400000
developer18ec8d62020-11-12 16:35:52 +0800[diff] [blame]14
developer18ec8d62020-11-12 16:35:52 +0800[diff] [blame]15/* SPL */
developer18ec8d62020-11-12 16:35:52 +0800[diff] [blame]16
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]17#define CFG_SYS_UBOOT_START CONFIG_TEXT_BASE
developer18ec8d62020-11-12 16:35:52 +0800[diff] [blame]18
19/* Dummy value */
Tom Rini6a5dccc2022-11-16 13:10:41 -0500[diff] [blame]20#define CFG_SYS_UBOOT_BASE 0
developer18ec8d62020-11-12 16:35:52 +0800[diff] [blame]21
22#endif /* __CONFIG_MT7620_H */