Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Heiko Schocher | 3757e97 | 2013-12-02 07:47:23 +0100 | [diff] [blame] | 2 | /* |
| 3 | * Common board functions for siemens AT91SAM9G45 based boards |
| 4 | * (C) Copyright 2013 Siemens AG |
| 5 | * |
| 6 | * Based on: |
| 7 | * U-Boot file: include/configs/at91sam9m10g45ek.h |
| 8 | * (C) Copyright 2007-2008 |
| 9 | * Stelian Pop <stelian@popies.net> |
| 10 | * Lead Tech Design <www.leadtechdesign.com> |
Heiko Schocher | 3757e97 | 2013-12-02 07:47:23 +0100 | [diff] [blame] | 11 | */ |
| 12 | |
| 13 | #ifndef __CONFIG_H |
| 14 | #define __CONFIG_H |
| 15 | |
| 16 | #include <asm/hardware.h> |
Heiko Schocher | 8189a08 | 2015-08-21 11:28:19 +0200 | [diff] [blame] | 17 | #include <linux/sizes.h> |
Heiko Schocher | 3757e97 | 2013-12-02 07:47:23 +0100 | [diff] [blame] | 18 | |
Heiko Schocher | 3757e97 | 2013-12-02 07:47:23 +0100 | [diff] [blame] | 19 | /* |
Simon Glass | 72cc538 | 2022-10-20 18:22:39 -0600 | [diff] [blame] | 20 | * Warning: changing CONFIG_TEXT_BASE requires |
Heiko Schocher | 3757e97 | 2013-12-02 07:47:23 +0100 | [diff] [blame] | 21 | * adapting the initial boot program. |
| 22 | * Since the linker has to swallow that define, we must use a pure |
| 23 | * hex number here! |
| 24 | */ |
| 25 | |
Heiko Schocher | 3757e97 | 2013-12-02 07:47:23 +0100 | [diff] [blame] | 26 | /* ARM asynchronous clock */ |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 27 | #define CFG_SYS_AT91_SLOW_CLOCK 32768 |
| 28 | #define CFG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ |
Heiko Schocher | 3757e97 | 2013-12-02 07:47:23 +0100 | [diff] [blame] | 29 | |
Heiko Schocher | 3757e97 | 2013-12-02 07:47:23 +0100 | [diff] [blame] | 30 | /* serial console */ |
Tom Rini | 7abe2a9 | 2022-12-04 10:14:02 -0500 | [diff] [blame] | 31 | #define CFG_USART_BASE ATMEL_BASE_DBGU |
Tom Rini | e111a12 | 2022-12-04 10:14:03 -0500 | [diff] [blame] | 32 | #define CFG_USART_ID ATMEL_ID_SYS |
Heiko Schocher | 3757e97 | 2013-12-02 07:47:23 +0100 | [diff] [blame] | 33 | |
Heiko Schocher | 3757e97 | 2013-12-02 07:47:23 +0100 | [diff] [blame] | 34 | /* SDRAM */ |
Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 35 | #define CFG_SYS_SDRAM_BASE ATMEL_BASE_CS6 |
| 36 | #define CFG_SYS_SDRAM_SIZE 0x08000000 |
Heiko Schocher | 3757e97 | 2013-12-02 07:47:23 +0100 | [diff] [blame] | 37 | |
Heiko Schocher | 3757e97 | 2013-12-02 07:47:23 +0100 | [diff] [blame] | 38 | /* NAND flash */ |
| 39 | #ifdef CONFIG_CMD_NAND |
Tom Rini | b421349 | 2022-11-12 17:36:51 -0500 | [diff] [blame] | 40 | #define CFG_SYS_NAND_BASE ATMEL_BASE_CS3 |
Heiko Schocher | 3757e97 | 2013-12-02 07:47:23 +0100 | [diff] [blame] | 41 | /* our ALE is AD21 */ |
Tom Rini | b421349 | 2022-11-12 17:36:51 -0500 | [diff] [blame] | 42 | #define CFG_SYS_NAND_MASK_ALE (1 << 21) |
Heiko Schocher | 3757e97 | 2013-12-02 07:47:23 +0100 | [diff] [blame] | 43 | /* our CLE is AD22 */ |
Tom Rini | b421349 | 2022-11-12 17:36:51 -0500 | [diff] [blame] | 44 | #define CFG_SYS_NAND_MASK_CLE (1 << 22) |
| 45 | #define CFG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 |
| 46 | #define CFG_SYS_NAND_READY_PIN AT91_PIN_PC8 |
Heiko Schocher | 3757e97 | 2013-12-02 07:47:23 +0100 | [diff] [blame] | 47 | #endif |
| 48 | |
Heiko Schocher | 08c5df2 | 2015-08-21 11:28:20 +0200 | [diff] [blame] | 49 | /* DFU class support */ |
Heiko Schocher | 08c5df2 | 2015-08-21 11:28:20 +0200 | [diff] [blame] | 50 | #define DFU_MANIFEST_POLL_TIMEOUT 25000 |
| 51 | |
Heiko Schocher | 3757e97 | 2013-12-02 07:47:23 +0100 | [diff] [blame] | 52 | /* bootstrap + u-boot + env in nandflash */ |
Heiko Schocher | 3757e97 | 2013-12-02 07:47:23 +0100 | [diff] [blame] | 53 | |
Heiko Schocher | 25d74a3 | 2014-10-31 08:31:06 +0100 | [diff] [blame] | 54 | /* Defines for SPL */ |
Heiko Schocher | 25d74a3 | 2014-10-31 08:31:06 +0100 | [diff] [blame] | 55 | |
Tom Rini | b421349 | 2022-11-12 17:36:51 -0500 | [diff] [blame] | 56 | #define CFG_SYS_NAND_U_BOOT_SIZE 0x80000 |
| 57 | #define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE |
| 58 | #define CFG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE |
Heiko Schocher | 25d74a3 | 2014-10-31 08:31:06 +0100 | [diff] [blame] | 59 | |
Tom Rini | b421349 | 2022-11-12 17:36:51 -0500 | [diff] [blame] | 60 | #define CFG_SYS_NAND_ECCSIZE 256 |
| 61 | #define CFG_SYS_NAND_ECCBYTES 3 |
| 62 | #define CFG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \ |
Heiko Schocher | 25d74a3 | 2014-10-31 08:31:06 +0100 | [diff] [blame] | 63 | 48, 49, 50, 51, 52, 53, 54, 55, \ |
| 64 | 56, 57, 58, 59, 60, 61, 62, 63, } |
| 65 | |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 66 | #define CFG_SYS_MASTER_CLOCK 132096000 |
Heiko Schocher | 25d74a3 | 2014-10-31 08:31:06 +0100 | [diff] [blame] | 67 | #define AT91_PLL_LOCK_TIMEOUT 1000000 |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 68 | #define CFG_SYS_AT91_PLLA 0x20c73f03 |
| 69 | #define CFG_SYS_MCKR 0x1301 |
| 70 | #define CFG_SYS_MCKR_CSS 0x1302 |
Heiko Schocher | 25d74a3 | 2014-10-31 08:31:06 +0100 | [diff] [blame] | 71 | |
Heiko Schocher | 3757e97 | 2013-12-02 07:47:23 +0100 | [diff] [blame] | 72 | #endif |