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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Masahiro Yamada24edb7e2015-02-10 21:37:01 +09002/* Copyright (C) 1994, 1995, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
3 2004, 2005
4 Free Software Foundation, Inc.
Masahiro Yamada24edb7e2015-02-10 21:37:01 +09005 */
6
7!! libgcc routines for the Renesas / SuperH SH CPUs.
8!! Contributed by Steve Chamberlain.
9!! sac@cygnus.com
10
11 .balign 4
12 .global __udivsi3
13 .type __udivsi3, @function
14div8:
15 div1 r5,r4
16div7:
17 div1 r5,r4; div1 r5,r4; div1 r5,r4
18 div1 r5,r4; div1 r5,r4; div1 r5,r4; rts; div1 r5,r4
19
20divx4:
21 div1 r5,r4; rotcl r0
22 div1 r5,r4; rotcl r0
23 div1 r5,r4; rotcl r0
24 rts; div1 r5,r4
25
26__udivsi3:
27 sts.l pr,@-r15
28 extu.w r5,r0
29 cmp/eq r5,r0
30 bf/s large_divisor
31 div0u
32 swap.w r4,r0
33 shlr16 r4
34 bsr div8
35 shll16 r5
36 bsr div7
37 div1 r5,r4
38 xtrct r4,r0
39 xtrct r0,r4
40 bsr div8
41 swap.w r4,r4
42 bsr div7
43 div1 r5,r4
44 lds.l @r15+,pr
45 xtrct r4,r0
46 swap.w r0,r0
47 rotcl r0
48 rts
49 shlr16 r5
50
51large_divisor:
52 mov #0,r0
53 xtrct r4,r0
54 xtrct r0,r4
55 bsr divx4
56 rotcl r0
57 bsr divx4
58 rotcl r0
59 bsr divx4
60 rotcl r0
61 bsr divx4
62 rotcl r0
63 lds.l @r15+,pr
64 rts
65 rotcl r0