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git01.mediatek.com / filogic / uboot / 3a812256c5f3d5ed7aa1a086ec2b180fba607197 / . / board / cloudengines / pogo_v4 / pogo_v4.c
blob: 61ce0d59c77e3d3a059fd96a3bfbf6c0a7ef4c25 [file] [log] [blame]
Tony Dinh6e36f662022-01-23 22:17:12 -0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2014-2022 Tony Dinh <mibodhi@gmail.com>
4 *
5 * Based on
6 * Copyright (C) 2012 David Purdy <david.c.purdy@gmail.com>
7 *
8 * Based on Kirkwood support:
9 * (C) Copyright 2009
10 * Marvell Semiconductor <www.marvell.com>
11 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
12 */
13
14#include <common.h>
15#include <netdev.h>
16#include <asm/arch/cpu.h>
17#include <asm/arch/soc.h>
18#include <asm/arch/mpp.h>
19#include <asm/io.h>
20#include <asm/arch/gpio.h>
21#include <asm/mach-types.h>
22#include <bootstage.h>
23#include <command.h>
24#include <init.h>
25#include <linux/bitops.h>
26
27DECLARE_GLOBAL_DATA_PTR;
28
29/* GPIO configuration */
30#define POGO_V4_OE_LOW (~(0))
31#define POGO_V4_OE_HIGH (~(0))
32#define POGO_V4_OE_VAL_LOW BIT(29)
33#define POGO_V4_OE_VAL_HIGH 0
34
35/* button */
36#define BTN_EJECT 29
37
38int board_early_init_f(void)
39{
40 /*
41 * default gpio configuration
42 * There are maximum 64 gpios controlled through 2 sets of registers
43 * the below configuration configures mainly initial LED status
44 */
45 mvebu_config_gpio(POGO_V4_OE_VAL_LOW,
46 POGO_V4_OE_VAL_HIGH,
47 POGO_V4_OE_LOW, POGO_V4_OE_HIGH);
48
49 /* Multi-Purpose Pins Functionality configuration */
50 u32 kwmpp_config[] = {
51 MPP0_NF_IO2,
52 MPP1_NF_IO3,
53 MPP2_NF_IO4,
54 MPP3_NF_IO5,
55 MPP4_NF_IO6,
56 MPP5_NF_IO7,
57 MPP6_SYSRST_OUTn,
58 MPP7_GPO,
59 MPP8_TW_SDA,
60 MPP9_TW_SCK,
61 MPP10_UART0_TXD,
62 MPP11_UART0_RXD,
63 MPP12_SD_CLK,
64 MPP13_SD_CMD,
65 MPP14_SD_D0,
66 MPP15_SD_D1,
67 MPP16_SD_D2,
68 MPP17_SD_D3,
69 MPP18_NF_IO0,
70 MPP19_NF_IO1,
71 MPP20_SATA1_ACTn,
72 MPP21_SATA0_ACTn,
73 MPP22_GPIO, /* Green LED */
74 MPP23_GPIO,
75 MPP24_GPIO, /* Red LED */
76 MPP25_GPIO,
77 MPP26_GPIO,
78 MPP27_GPIO,
79 MPP28_GPIO,
80 MPP29_GPIO, /* Eject button */
81 MPP30_GPIO,
82 MPP31_GPIO,
83 MPP32_GPIO,
84 MPP33_GPIO,
85 MPP34_GPIO,
86 MPP35_GPIO, /* FR6192 has only 36 GPIOs */
87 0
88 };
89 kirkwood_mpp_conf(kwmpp_config, NULL);
90
91 return 0;
92}
93
94int board_eth_init(struct bd_info *bis)
95{
96 return cpu_eth_init(bis);
97}
98
99int board_late_init(void)
100{
101 /* Do late init to ensure successful enumeration of XHCI devices */
102 pci_init();
103 return 0;
104}
105
106int board_init(void)
107{
108 /* Boot parameters address */
109 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
110
111 return 0;
112}
113
114#if CONFIG_IS_ENABLED(BOOTSTAGE)
115#define GREEN_LED BIT(22)
116#define RED_LED BIT(24)
117#define BOTH_LEDS (GREEN_LED | RED_LED)
118#define NEITHER_LED 0
119
120static void set_leds(u32 leds, u32 blinking)
121{
122 struct kwgpio_registers *r;
123 u32 oe;
124 u32 bl;
125
126 r = (struct kwgpio_registers *)MVEBU_GPIO0_BASE;
127 oe = readl(&r->oe) | BOTH_LEDS;
128 writel(oe & ~leds, &r->oe); /* active low */
129 bl = readl(&r->blink_en) & ~BOTH_LEDS;
130 writel(bl | blinking, &r->blink_en);
131}
132
133void show_boot_progress(int val)
134{
135 switch (val) {
136 case BOOTSTAGE_ID_RUN_OS: /* booting Linux */
137 set_leds(BOTH_LEDS, NEITHER_LED);
138 break;
139 case BOOTSTAGE_ID_NET_ETH_START: /* Ethernet initialization */
140 set_leds(GREEN_LED, GREEN_LED);
141 break;
142 default:
143 if (val < 0) /* error */
144 set_leds(RED_LED, RED_LED);
145 break;
146 }
147}
148#endif