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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Patrick Bruennba81b042016-11-04 11:57:02 +01002/*
3 * Copyright (C) 2015 Beckhoff Automation GmbH & Co. KG
4 * Patrick Bruenn <p.bruenn@beckhoff.com>
5 *
6 * Configuration settings for Beckhoff CX9020.
7 *
8 * Based on Freescale's Linux i.MX mx53loco.h file:
9 * Copyright (C) 2010-2011 Freescale Semiconductor.
Patrick Bruennba81b042016-11-04 11:57:02 +010010 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15#include <asm/arch/imx-regs.h>
16
Patrick Bruennba81b042016-11-04 11:57:02 +010017#define CONFIG_MXC_UART_BASE UART2_BASE
18
19#define CONFIG_FPGA_COUNT 1
20
21/* MMC Configs */
Patrick Bruennba81b042016-11-04 11:57:02 +010022#define CONFIG_SYS_FSL_ESDHC_ADDR 0
23#define CONFIG_SYS_FSL_ESDHC_NUM 2
24
Patrick Bruennba81b042016-11-04 11:57:02 +010025/* bootz: zImage/initrd.img support */
Patrick Bruennba81b042016-11-04 11:57:02 +010026
Patrick Bruennba81b042016-11-04 11:57:02 +010027
28/* USB Configs */
Patrick Bruennba81b042016-11-04 11:57:02 +010029#define CONFIG_MXC_USB_PORT 1
30#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
31#define CONFIG_MXC_USB_FLAGS 0
32
Patrick Bruennba81b042016-11-04 11:57:02 +010033/* Command definition */
Patrick Bruennba81b042016-11-04 11:57:02 +010034
Steffen Dirkwinkelab0ed602019-10-23 07:40:43 +020035#define BOOT_TARGET_DEVICES(func) \
36 func(MMC, mmc, 0) \
37 func(MMC, mmc, 1) \
38 func(USB, usb, 0) \
39 func(PXE, pxe, na)
40
41#include <config_distro_bootcmd.h>
42
Patrick Bruennba81b042016-11-04 11:57:02 +010043#define CONFIG_EXTRA_ENV_SETTINGS \
Steffen Dirkwinkelab0ed602019-10-23 07:40:43 +020044 "fdt_addr_r=0x75000000\0" \
Patrick Bruenn2ef943e2017-07-11 11:23:21 +020045 "pxefile_addr_r=0x73000000\0" \
Steffen Dirkwinkelab0ed602019-10-23 07:40:43 +020046 "scriptaddr=0x74000000\0" \
47 "ramdisk_addr_r=0x80000000\0" \
48 "kernel_addr_r=0x72000000\0" \
49 "fdt_high=0xffffffff\0" \
Patrick Bruennba81b042016-11-04 11:57:02 +010050 "console=ttymxc1,115200\0" \
Steffen Dirkwinkela2cab662019-10-23 07:40:42 +020051 "stdin=serial\0" \
52 "stdout=serial,vidconsole\0" \
53 "stderr=serial,vidconsole\0" \
Steffen Dirkwinkelab0ed602019-10-23 07:40:43 +020054 "fdtfile=imx53-cx9020.dtb\0" \
55 BOOTENV
Patrick Bruennba81b042016-11-04 11:57:02 +010056
57#define CONFIG_ARP_TIMEOUT 200UL
58
59/* Miscellaneous configurable options */
Patrick Bruennba81b042016-11-04 11:57:02 +010060#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
61
Patrick Bruennba81b042016-11-04 11:57:02 +010062/* Physical Memory Map */
Patrick Bruennba81b042016-11-04 11:57:02 +010063#define PHYS_SDRAM_1 CSD0_BASE_ADDR
64#define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size)
65#define PHYS_SDRAM_2 CSD1_BASE_ADDR
66#define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size)
67#define PHYS_SDRAM_SIZE (gd->ram_size)
68
69#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1)
70#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR)
71#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE)
72
73#define CONFIG_SYS_INIT_SP_OFFSET \
74 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
75#define CONFIG_SYS_INIT_SP_ADDR \
76 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
77
Masahiro Yamada8cea9b52017-02-11 22:43:54 +090078/* environment organization */
Patrick Bruennba81b042016-11-04 11:57:02 +010079
80/* Framebuffer and LCD */
Steffen Dirkwinkel31736182019-04-17 13:57:17 +020081#define CONFIG_IMX_VIDEO_SKIP
Patrick Bruennba81b042016-11-04 11:57:02 +010082
83#endif /* __CONFIG_H */