blob: 2449a987953ccb13d671ea630dbc895ac82bc492 [file] [log] [blame]
Heiko Thiery05a3d952022-01-31 17:30:45 +01001/* SPDX-License-Identifier: GPL-2.0+ */
2
3#ifndef __KONTRON_PITX_IMX8M_H
4#define __KONTRON_PITX_IMX8M_H
5
6#include <linux/sizes.h>
7#include <linux/stringify.h>
8#include <asm/arch/imx-regs.h>
9
10#define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M)
11
12#define CONFIG_SPL_MAX_SIZE (124 * SZ_1K)
13#define CONFIG_SYS_MONITOR_LEN (512 * SZ_1K)
Heiko Thiery05a3d952022-01-31 17:30:45 +010014
15#ifdef CONFIG_SPL_BUILD
Heiko Thiery05a3d952022-01-31 17:30:45 +010016#define CONFIG_SPL_STACK 0x187FF0
17#define CONFIG_SPL_BSS_START_ADDR 0x00180000
18#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K
19#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
20#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K
21#define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000
22
23/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
24#define CONFIG_MALLOC_F_ADDR 0x182000
25/* For RAW image gives a error info not panic */
26#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
27
28
29#define CONFIG_POWER_PFUZE100
30#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
31#endif
32
Heiko Thiery05a3d952022-01-31 17:30:45 +010033/* ENET1 Config */
34#if defined(CONFIG_CMD_NET)
35#define CONFIG_ETHPRIME "FEC"
36
37#define CONFIG_FEC_XCV_TYPE RGMII
38#define CONFIG_FEC_MXC_PHYADDR 0
39#define FEC_QUIRK_ENET_MAC
40
41#define IMX_FEC_BASE 0x30BE0000
42#define PHY_ANEG_TIMEOUT 20000
43
44#endif
45
46#define ENV_MEM_LAYOUT_SETTINGS \
47 "kernel_addr_r=0x40880000\0" \
48 "fdt_addr_r=0x43000000\0" \
49 "scriptaddr=0x43500000\0" \
50 "initrd_addr=0x43800000\0" \
51 "pxefile_addr_r=0x43500000\0" \
52 "bootm_size=0x10000000\0" \
53
54#define BOOT_TARGET_DEVICES(func) \
55 func(MMC, mmc, 0) \
56 func(MMC, mmc, 1) \
57 func(USB, usb, 0) \
58 func(DHCP, dhcp, na) \
59 func(PXE, pxe, 0)
60
61#include <config_distro_bootcmd.h>
62
63/* Initial environment variables */
64#define CONFIG_EXTRA_ENV_SETTINGS \
65 "image=Image\0" \
66 "console=ttymxc2,115200\0" \
67 "boot_fdt=try\0" \
68 "fdtfile=freescale/imx8mq-kontron-pitx-imx8m.dtb\0" \
69 "dfu_alt_info=mmc 0=flash-bin raw 0x42 0x1000 mmcpart 1\0"\
70 ENV_MEM_LAYOUT_SETTINGS \
71 BOOTENV
72
73
74#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
75#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
76#define CONFIG_SYS_INIT_SP_OFFSET \
77 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
78#define CONFIG_SYS_INIT_SP_ADDR \
79 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
80
81#define CONFIG_SYS_SDRAM_BASE 0x40000000
82#define PHYS_SDRAM 0x40000000
83#define PHYS_SDRAM_SIZE 0xC0000000 /* 3GB DDR */
84
85#define CONFIG_MXC_UART_BASE UART3_BASE_ADDR
86
87#define CONFIG_SYS_FSL_USDHC_NUM 2
88#define CONFIG_SYS_FSL_ESDHC_ADDR 0
89
Heiko Thiery05a3d952022-01-31 17:30:45 +010090#endif