blob: 9d3ee7f2245871a411d3a500cce8401988c8bf91 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
wdenkc4cbd342005-01-09 18:21:42 +00002/*
3 * Configuation settings for the Sentec Cobra Board.
4 *
5 * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
wdenkc4cbd342005-01-09 18:21:42 +00006 */
7
8/* ---
Bin Meng75574052016-02-05 19:30:11 -08009 * Version: U-Boot 1.0.0 - initial release for Sentec COBRA5272 board
wdenkc4cbd342005-01-09 18:21:42 +000010 * Date: 2004-03-29
11 * Author: Florian Schlote
12 *
13 * For a description of configuration options please refer also to the
14 * general u-boot-1.x.x/README file
15 * ---
16 */
17
18/* ---
19 * board/config.h - configuration options, board specific
20 * ---
21 */
22
23#ifndef _CONFIG_COBRA5272_H
24#define _CONFIG_COBRA5272_H
25
26/* ---
wdenkc4cbd342005-01-09 18:21:42 +000027 * Defines processor clock - important for correct timings concerning serial
28 * interface etc.
wdenkc4cbd342005-01-09 18:21:42 +000029 * ---
30 */
31
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020032#define CONFIG_SYS_CLK 66000000
33#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
wdenkc4cbd342005-01-09 18:21:42 +000034
TsiChungLiewcfa2b482007-08-15 19:41:06 -050035/* Enable Dma Timer */
36#define CONFIG_MCFTMR
wdenkc4cbd342005-01-09 18:21:42 +000037
38/* ---
39 * Define baudrate for UART1 (console output, tftp, ...)
40 * default value of CONFIG_BAUDRATE for Sentec board: 19200 baud
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020041 * CONFIG_SYS_BAUDRATE_TABLE defines values that can be selected in u-boot command
wdenkc4cbd342005-01-09 18:21:42 +000042 * interface
43 * ---
44 */
45
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020046#define CONFIG_SYS_UART_PORT (0)
wdenkc4cbd342005-01-09 18:21:42 +000047
48/* ---
49 * set "#if 0" to "#if 1" if (Hardware)-WATCHDOG should be enabled & change
50 * timeout acc. to your needs
51 * #define CONFIG_WATCHDOG_TIMEOUT x , x is timeout in milliseconds, e. g. 10000
52 * for 10 sec
53 * ---
54 */
55
56#if 0
wdenkc4cbd342005-01-09 18:21:42 +000057#define CONFIG_WATCHDOG_TIMEOUT 10000 /* timeout in milliseconds */
58#endif
59
60/* ---
61 * CONFIG_MONITOR_IS_IN_RAM defines if u-boot is started from a different
62 * bootloader residing in flash ('chainloading'); if you want to use
63 * chainloading or want to compile a u-boot binary that can be loaded into
64 * RAM via BDM set
Wolfgang Denka1be4762008-05-20 16:00:29 +020065 * "#if 0" to "#if 1"
wdenkc4cbd342005-01-09 18:21:42 +000066 * You will need a first stage bootloader then, e. g. colilo or a working BDM
67 * cable (Background Debug Mode)
68 *
69 * Setting #if 0: u-boot will start from flash and relocate itself to RAM
70 *
Wolfgang Denk0708bc62010-10-07 21:51:12 +020071 * Please do not forget to modify the setting of CONFIG_SYS_TEXT_BASE
wdenkc4cbd342005-01-09 18:21:42 +000072 * in board/cobra5272/config.mk accordingly (#if 0: 0xffe00000; #if 1: 0x20000)
73 *
74 * ---
75 */
76
77#if 0
78#define CONFIG_MONITOR_IS_IN_RAM /* monitor is started from a preloader */
79#endif
80
81/* ---
82 * Configuration for environment
83 * Environment is embedded in u-boot in the second sector of the flash
84 * ---
85 */
86
angelo@sysam.it6312a952015-03-29 22:54:16 +020087#define LDS_BOARD_TEXT \
Simon Glass547cb402017-08-03 12:21:49 -060088 . = DEFINED(env_offset) ? env_offset : .; \
89 env/embedded.o(.text);
Jon Loeliger37ec35e2007-07-04 22:31:56 -050090
TsiChungLiewcfa2b482007-08-15 19:41:06 -050091#ifdef CONFIG_MCFFEC
TsiChung Liewb3162452008-03-30 01:22:13 -050092# define CONFIG_MII_INIT 1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020093# define CONFIG_SYS_DISCOVER_PHY
94# define CONFIG_SYS_RX_ETH_BUFFER 8
95# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020096/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
97# ifndef CONFIG_SYS_DISCOVER_PHY
TsiChungLiewcfa2b482007-08-15 19:41:06 -050098# define FECDUPLEX FULL
99# define FECSPEED _100BASET
100# else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200101# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
102# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
TsiChungLiewcfa2b482007-08-15 19:41:06 -0500103# endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200104# endif /* CONFIG_SYS_DISCOVER_PHY */
TsiChungLiewcfa2b482007-08-15 19:41:06 -0500105#endif
wdenkc4cbd342005-01-09 18:21:42 +0000106
107/*
108 *-----------------------------------------------------------------------------
109 * Define user parameters that have to be customized most likely
110 *-----------------------------------------------------------------------------
111 */
112
113/*AUTOBOOT settings - booting images automatically by u-boot after power on*/
114
wdenkc4cbd342005-01-09 18:21:42 +0000115/* The following settings will be contained in the environment block ; if you
116want to use a neutral environment all those settings can be manually set in
117u-boot: 'set' command */
118
119#if 0
120
wdenkc4cbd342005-01-09 18:21:42 +0000121enter a valid image address in flash */
122
wdenkc4cbd342005-01-09 18:21:42 +0000123/* User network settings */
124
wdenkc4cbd342005-01-09 18:21:42 +0000125#define CONFIG_IPADDR 192.168.100.2 /* default board IP address */
126#define CONFIG_SERVERIP 192.168.100.1 /* default tftp server IP address */
127
128#endif
129
wdenkc4cbd342005-01-09 18:21:42 +0000130/*---*/
131
wdenkc4cbd342005-01-09 18:21:42 +0000132/*
133 *-----------------------------------------------------------------------------
134 * End of user parameters to be customized
135 *-----------------------------------------------------------------------------
136 */
137
138/* ---
139 * Defines memory range for test
140 * ---
141 */
142
wdenkc4cbd342005-01-09 18:21:42 +0000143/* ---
144 * Low Level Configuration Settings
145 * (address mappings, register initial values, etc.)
146 * You should know what you are doing if you make changes here.
147 * ---
148 */
149
150/* ---
151 * Base register address
152 * ---
153 */
154
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200155#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */
wdenkc4cbd342005-01-09 18:21:42 +0000156
157/* ---
158 * System Conf. Reg. & System Protection Reg.
159 * ---
160 */
161
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200162#define CONFIG_SYS_SCR 0x0003
163#define CONFIG_SYS_SPR 0xffff
wdenkc4cbd342005-01-09 18:21:42 +0000164
165/* ---
166 * Ethernet settings
167 * ---
168 */
169
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200170#define CONFIG_SYS_DISCOVER_PHY
171#define CONFIG_SYS_ENET_BD_BASE 0x780000
wdenkc4cbd342005-01-09 18:21:42 +0000172
173/*-----------------------------------------------------------------------
174 * Definitions for initial stack pointer and data area (in internal SRAM)
175 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200176#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200177#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
Wolfgang Denk0191e472010-10-26 14:34:52 +0200178#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200179#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkc4cbd342005-01-09 18:21:42 +0000180
181/*-----------------------------------------------------------------------
182 * Start addresses for the final memory configuration
183 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200184 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenkc4cbd342005-01-09 18:21:42 +0000185 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200186#define CONFIG_SYS_SDRAM_BASE 0x00000000
wdenkc4cbd342005-01-09 18:21:42 +0000187
188/*
189 *-------------------------------------------------------------------------
190 * RAM SIZE (is defined above)
191 *-----------------------------------------------------------------------
192 */
193
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200194/* #define CONFIG_SYS_SDRAM_SIZE 16 */
wdenkc4cbd342005-01-09 18:21:42 +0000195
196/*
197 *-----------------------------------------------------------------------
198 */
199
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200200#define CONFIG_SYS_FLASH_BASE 0xffe00000
wdenkc4cbd342005-01-09 18:21:42 +0000201
202#ifdef CONFIG_MONITOR_IS_IN_RAM
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200203#define CONFIG_SYS_MONITOR_BASE 0x20000
wdenkc4cbd342005-01-09 18:21:42 +0000204#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200205#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
wdenkc4cbd342005-01-09 18:21:42 +0000206#endif
207
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200208#define CONFIG_SYS_MONITOR_LEN 0x20000
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200209#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
wdenkc4cbd342005-01-09 18:21:42 +0000210
211/*
212 * For booting Linux, the board info and command line data
213 * have to be in the first 8 MB of memory, since this is
214 * the maximum mapped by the Linux kernel during initialization ??
215 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200216#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkc4cbd342005-01-09 18:21:42 +0000217
218/*-----------------------------------------------------------------------
219 * FLASH organization
220 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200221#define CONFIG_SYS_MAX_FLASH_SECT 11 /* max number of sectors on one chip */
222#define CONFIG_SYS_FLASH_ERASE_TOUT 1000 /* flash timeout */
wdenkc4cbd342005-01-09 18:21:42 +0000223
224/*-----------------------------------------------------------------------
225 * Cache Configuration
226 */
wdenkc4cbd342005-01-09 18:21:42 +0000227
TsiChung Liew0ee47d42010-03-11 22:12:53 -0600228#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200229 CONFIG_SYS_INIT_RAM_SIZE - 8)
TsiChung Liew0ee47d42010-03-11 22:12:53 -0600230#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200231 CONFIG_SYS_INIT_RAM_SIZE - 4)
TsiChung Liew0ee47d42010-03-11 22:12:53 -0600232#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
233#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
234 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
235 CF_ACR_EN | CF_ACR_SM_ALL)
236#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
237 CF_CACR_DISD | CF_CACR_INVI | \
238 CF_CACR_CEIB | CF_CACR_DCM | \
239 CF_CACR_EUSP)
240
wdenkc4cbd342005-01-09 18:21:42 +0000241/*-----------------------------------------------------------------------
wdenkc4cbd342005-01-09 18:21:42 +0000242 * LED config
243 */
244#define LED_STAT_0 0xffff /*all LEDs off*/
245#define LED_STAT_1 0xfffe
246#define LED_STAT_2 0xfffd
247#define LED_STAT_3 0xfffb
248#define LED_STAT_4 0xfff7
249#define LED_STAT_5 0xffef
250#define LED_STAT_6 0xffdf
251#define LED_STAT_7 0xff00 /*all LEDs on*/
252
253/*-----------------------------------------------------------------------
254 * Port configuration (GPIO)
255 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200256#define CONFIG_SYS_PACNT 0x00000000 /* PortA control reg.: All pins are external
wdenkc4cbd342005-01-09 18:21:42 +0000257GPIO*/
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200258#define CONFIG_SYS_PADDR 0x00FF /* PortA direction reg.: PA7 to PA0 are outputs
wdenkc4cbd342005-01-09 18:21:42 +0000259(1^=output, 0^=input) */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200260#define CONFIG_SYS_PADAT LED_STAT_0 /* PortA value reg.: Turn all LED off */
261#define CONFIG_SYS_PBCNT 0x55554155 /* PortB control reg.: Ethernet/UART
wdenkc4cbd342005-01-09 18:21:42 +0000262configuration */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200263#define CONFIG_SYS_PBDDR 0x0000 /* PortB direction: All pins configured as inputs */
264#define CONFIG_SYS_PBDAT 0x0000 /* PortB value reg. */
265#define CONFIG_SYS_PDCNT 0x00000000 /* PortD control reg. */
wdenkc4cbd342005-01-09 18:21:42 +0000266
267#endif /* _CONFIG_COBRA5272_H */