blob: 747e73b17fcb982fbc45fd5b6be2e51a95272430 [file] [log] [blame]
Eugeniy Paltsev062da422019-10-08 19:29:30 +03001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * HSDK SoC Reset Controller driver
4 *
5 * Copyright (C) 2019 Synopsys, Inc. All rights reserved.
6 * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
7 */
8
Simon Glass0f2af882020-05-10 11:40:05 -06009#include <log.h>
Eugeniy Paltsev062da422019-10-08 19:29:30 +030010#include <asm/io.h>
Eugeniy Paltsev062da422019-10-08 19:29:30 +030011#include <dm.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -060012#include <linux/bitops.h>
Eugeniy Paltsev062da422019-10-08 19:29:30 +030013#include <linux/iopoll.h>
14#include <reset-uclass.h>
15
16struct hsdk_rst {
17 void __iomem *regs_ctl;
18 void __iomem *regs_rst;
19};
20
21static const u32 rst_map[] = {
22 BIT(16), /* APB_RST */
23 BIT(17), /* AXI_RST */
24 BIT(18), /* ETH_RST */
25 BIT(19), /* USB_RST */
26 BIT(20), /* SDIO_RST */
27 BIT(21), /* HDMI_RST */
28 BIT(22), /* GFX_RST */
29 BIT(25), /* DMAC_RST */
30 BIT(31), /* EBI_RST */
31};
32
33#define HSDK_MAX_RESETS ARRAY_SIZE(rst_map)
34
35#define CGU_SYS_RST_CTRL 0x0
36#define CGU_IP_SW_RESET 0x0
37#define CGU_IP_SW_RESET_DELAY_SHIFT 16
38#define CGU_IP_SW_RESET_DELAY_MASK GENMASK(31, CGU_IP_SW_RESET_DELAY_SHIFT)
39#define CGU_IP_SW_RESET_DELAY 0
40#define CGU_IP_SW_RESET_RESET BIT(0)
41#define SW_RESET_TIMEOUT 10000
42
43static void hsdk_reset_config(struct hsdk_rst *rst, unsigned long id)
44{
45 writel(rst_map[id], rst->regs_ctl + CGU_SYS_RST_CTRL);
46}
47
48static int hsdk_reset_do(struct hsdk_rst *rst)
49{
50 u32 reg;
51
52 reg = readl(rst->regs_rst + CGU_IP_SW_RESET);
53 reg &= ~CGU_IP_SW_RESET_DELAY_MASK;
54 reg |= CGU_IP_SW_RESET_DELAY << CGU_IP_SW_RESET_DELAY_SHIFT;
55 reg |= CGU_IP_SW_RESET_RESET;
56 writel(reg, rst->regs_rst + CGU_IP_SW_RESET);
57
58 /* wait till reset bit is back to 0 */
59 return readl_poll_timeout(rst->regs_rst + CGU_IP_SW_RESET, reg,
60 !(reg & CGU_IP_SW_RESET_RESET), SW_RESET_TIMEOUT);
61}
62
63static int hsdk_reset_reset(struct reset_ctl *rst_ctl)
64{
65 struct udevice *dev = rst_ctl->dev;
66 struct hsdk_rst *rst = dev_get_priv(dev);
67
68 if (rst_ctl->id >= HSDK_MAX_RESETS)
69 return -EINVAL;
70
71 debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, rst_ctl,
72 rst_ctl->dev, rst_ctl->id);
73
74 hsdk_reset_config(rst, rst_ctl->id);
75 return hsdk_reset_do(rst);
76}
77
Eugeniy Paltsev062da422019-10-08 19:29:30 +030078static const struct reset_ops hsdk_reset_ops = {
Eugeniy Paltsev062da422019-10-08 19:29:30 +030079 .rst_deassert = hsdk_reset_reset,
80};
81
82static const struct udevice_id hsdk_reset_dt_match[] = {
83 { .compatible = "snps,hsdk-reset" },
84 { },
85};
86
87static int hsdk_reset_probe(struct udevice *dev)
88{
89 struct hsdk_rst *rst = dev_get_priv(dev);
90
91 rst->regs_ctl = dev_remap_addr_index(dev, 0);
92 if (!rst->regs_ctl)
93 return -EINVAL;
94
95 rst->regs_rst = dev_remap_addr_index(dev, 1);
96 if (!rst->regs_rst)
97 return -EINVAL;
98
99 return 0;
100}
101
102U_BOOT_DRIVER(hsdk_reset) = {
103 .name = "hsdk-reset",
104 .id = UCLASS_RESET,
105 .of_match = hsdk_reset_dt_match,
106 .ops = &hsdk_reset_ops,
107 .probe = hsdk_reset_probe,
Simon Glass8a2b47f2020-12-03 16:55:17 -0700108 .priv_auto = sizeof(struct hsdk_rst),
Eugeniy Paltsev062da422019-10-08 19:29:30 +0300109};