blob: 02e8f8eb1fed9c64e49d99017cb6debae2023c32 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Marcel Ziswiler11e2a532014-09-05 10:18:38 +02002/*
Marcel Ziswiler97d34492018-05-09 00:18:40 +02003 * (C) Copyright 2014-2018
Marcel Ziswiler11e2a532014-09-05 10:18:38 +02004 * Marcel Ziswiler <marcel@ziswiler.com>
Marcel Ziswiler11e2a532014-09-05 10:18:38 +02005 */
6
Marcel Ziswiler61c99fe2022-05-21 12:42:46 +02007#include <env.h>
Simon Glass97589732020-05-10 11:40:02 -06008#include <init.h>
Simon Glass0f2af882020-05-10 11:40:05 -06009#include <log.h>
Marcel Ziswiler11e2a532014-09-05 10:18:38 +020010#include <asm/arch/gp_padctrl.h>
11#include <asm/arch/pinmux.h>
Marcel Ziswilerdd899d02015-08-06 00:47:00 +020012#include <asm/arch-tegra/ap.h>
13#include <asm/arch-tegra/tegra.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060014#include <asm/global_data.h>
Marcel Ziswiler11e2a532014-09-05 10:18:38 +020015#include <asm/gpio.h>
Marcel Ziswilerdd899d02015-08-06 00:47:00 +020016#include <asm/io.h>
Marcel Ziswiler764d4122015-08-06 00:47:10 +020017#include <dm.h>
Marcel Ziswiler11e2a532014-09-05 10:18:38 +020018#include <i2c.h>
Marcel Ziswiler61c99fe2022-05-21 12:42:46 +020019#include <fdt_support.h>
Marcel Ziswiler97d34492018-05-09 00:18:40 +020020#include <pci_tegra.h>
Simon Glassdbd79542020-05-10 11:40:11 -060021#include <linux/delay.h>
Stefan Agner98ffd0f2016-11-30 13:41:53 -080022#include "../common/tdx-common.h"
Marcel Ziswiler11e2a532014-09-05 10:18:38 +020023
24#include "pinmux-config-apalis_t30.h"
25
Marcel Ziswilerd92dee52016-11-16 17:49:23 +010026DECLARE_GLOBAL_DATA_PTR;
27
Marcel Ziswiler11e2a532014-09-05 10:18:38 +020028#define PMU_I2C_ADDRESS 0x2D
29#define MAX_I2C_RETRY 3
30
Marcel Ziswiler97d34492018-05-09 00:18:40 +020031#ifdef CONFIG_APALIS_T30_PCIE_EVALBOARD_INIT
32#define PEX_PERST_N TEGRA_GPIO(S, 7) /* Apalis GPIO7 */
33#define RESET_MOCI_CTRL TEGRA_GPIO(I, 4)
34
35static int pci_reset_status;
36#endif /* CONFIG_APALIS_T30_PCIE_EVALBOARD_INIT */
37
Marcel Ziswilerdd899d02015-08-06 00:47:00 +020038int arch_misc_init(void)
39{
40 if (readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BOOTTYPE) ==
41 NVBOOTTYPE_RECOVERY)
42 printf("USB recovery mode\n");
43
44 return 0;
45}
46
Stefan Agner98ffd0f2016-11-30 13:41:53 -080047#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
Masahiro Yamadaf7ed78b2020-06-26 15:13:33 +090048int ft_board_setup(void *blob, struct bd_info *bd)
Stefan Agner98ffd0f2016-11-30 13:41:53 -080049{
Marcel Ziswiler61c99fe2022-05-21 12:42:46 +020050 u8 enetaddr[6];
51
52 /* MAC addr */
53 if (eth_env_get_enetaddr("ethaddr", enetaddr)) {
54 int err = fdt_find_and_setprop(blob,
55 "/pcie@3000/pci@3,0/ethernet@0,0",
56 "local-mac-address", enetaddr, 6, 0);
57
58 /* Older device trees might have used a different node name */
59 if (err < 0)
60 err = fdt_find_and_setprop(blob,
61 "/pcie@3000/pci@3,0/pcie@0",
62 "local-mac-address", enetaddr, 6, 0);
63
64 if (err >= 0)
65 puts(" MAC address updated...\n");
66 }
67
Stefan Agner98ffd0f2016-11-30 13:41:53 -080068 return ft_common_board_setup(blob, bd);
69}
70#endif
71
Marcel Ziswiler11e2a532014-09-05 10:18:38 +020072/*
73 * Routine: pinmux_init
74 * Description: Do individual peripheral pinmux configs
75 */
76void pinmux_init(void)
77{
78 pinmux_config_pingrp_table(tegra3_pinmux_common,
79 ARRAY_SIZE(tegra3_pinmux_common));
80
81 pinmux_config_pingrp_table(unused_pins_lowpower,
82 ARRAY_SIZE(unused_pins_lowpower));
83
84 /* Initialize any non-default pad configs (APB_MISC_GP regs) */
85 pinmux_config_drvgrp_table(apalis_t30_padctrl,
86 ARRAY_SIZE(apalis_t30_padctrl));
87}
88
89#ifdef CONFIG_PCI_TEGRA
90int tegra_pcie_board_init(void)
91{
Simon Glass667aee92014-12-10 08:55:57 -070092 struct udevice *dev;
Marcel Ziswiler11e2a532014-09-05 10:18:38 +020093 u8 addr, data[1];
94 int err;
95
Simon Glassa2723ae2015-01-25 08:26:55 -070096 err = i2c_get_chip_for_busnum(0, PMU_I2C_ADDRESS, 1, &dev);
Marcel Ziswiler11e2a532014-09-05 10:18:38 +020097 if (err) {
Simon Glass667aee92014-12-10 08:55:57 -070098 debug("%s: Cannot find PMIC I2C chip\n", __func__);
Marcel Ziswiler11e2a532014-09-05 10:18:38 +020099 return err;
100 }
Marcel Ziswiler764d4122015-08-06 00:47:10 +0200101
Marcel Ziswiler11e2a532014-09-05 10:18:38 +0200102 /* TPS659110: VDD2_OP_REG = 1.05V */
103 data[0] = 0x27;
104 addr = 0x25;
105
Simon Glass7d722762015-01-12 18:02:07 -0700106 err = dm_i2c_write(dev, addr, data, 1);
Marcel Ziswiler11e2a532014-09-05 10:18:38 +0200107 if (err) {
108 debug("failed to set VDD supply\n");
109 return err;
110 }
111
112 /* TPS659110: VDD2_REG 7.5 mV/us, ACTIVE */
113 data[0] = 0x0D;
114 addr = 0x24;
115
Simon Glass7d722762015-01-12 18:02:07 -0700116 err = dm_i2c_write(dev, addr, data, 1);
Marcel Ziswiler11e2a532014-09-05 10:18:38 +0200117 if (err) {
118 debug("failed to enable VDD supply\n");
119 return err;
120 }
121
122 /* TPS659110: LDO6_REG = 1.1V, ACTIVE */
123 data[0] = 0x0D;
124 addr = 0x35;
125
Simon Glass7d722762015-01-12 18:02:07 -0700126 err = dm_i2c_write(dev, addr, data, 1);
Marcel Ziswiler11e2a532014-09-05 10:18:38 +0200127 if (err) {
128 debug("failed to set AVDD supply\n");
129 return err;
130 }
131
Marcel Ziswiler97d34492018-05-09 00:18:40 +0200132#ifdef CONFIG_APALIS_T30_PCIE_EVALBOARD_INIT
133 gpio_request(PEX_PERST_N, "PEX_PERST_N");
134 gpio_request(RESET_MOCI_CTRL, "RESET_MOCI_CTRL");
135#endif /* CONFIG_APALIS_T30_PCIE_EVALBOARD_INIT */
136
Marcel Ziswiler11e2a532014-09-05 10:18:38 +0200137 return 0;
138}
Marcel Ziswiler97d34492018-05-09 00:18:40 +0200139
140void tegra_pcie_board_port_reset(struct tegra_pcie_port *port)
141{
142 int index = tegra_pcie_port_index_of_port(port);
143
144 if (index == 2) { /* I210 Gigabit Ethernet Controller (On-module) */
145 tegra_pcie_port_reset(port);
146 }
147#ifdef CONFIG_APALIS_T30_PCIE_EVALBOARD_INIT
148 /*
149 * Apalis PCIe aka port 1 and Apalis Type Specific 4 Lane PCIe aka port
150 * 0 share the same RESET_MOCI therefore only assert it once for both
151 * ports to avoid losing the previously brought up port again.
152 */
153 else if ((index == 1) || (index == 0)) {
154 /* only do it once per init cycle */
155 if (pci_reset_status % 2 == 0) {
156 /*
157 * Reset PLX PEX 8605 PCIe Switch plus PCIe devices on
158 * Apalis Evaluation Board
159 */
160 gpio_direction_output(PEX_PERST_N, 0);
161 gpio_direction_output(RESET_MOCI_CTRL, 0);
162
163 /*
164 * Must be asserted for 100 ms after power and clocks
165 * are stable
166 */
167 mdelay(100);
168
169 gpio_set_value(PEX_PERST_N, 1);
170 /*
171 * Err_5: PEX_REFCLK_OUTpx/nx Clock Outputs is not
172 * Guaranteed Until 900 us After PEX_PERST# De-assertion
173 */
174 mdelay(1);
175 gpio_set_value(RESET_MOCI_CTRL, 1);
176 }
177 pci_reset_status++;
178 }
179#endif /* CONFIG_APALIS_T30_PCIE_EVALBOARD_INIT */
180}
Marcel Ziswiler11e2a532014-09-05 10:18:38 +0200181#endif /* CONFIG_PCI_TEGRA */
Gerard Salvatella108d7392018-11-19 15:54:10 +0100182
183/*
184 * Backlight off before OS handover
185 */
186void board_preboot_os(void)
187{
188 gpio_request(TEGRA_GPIO(V, 2), "BKL1_ON");
189 gpio_direction_output(TEGRA_GPIO(V, 2), 0);
190}