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Masahiro Yamadabb2ff9d2014-10-03 19:21:06 +09001/*
Masahiro Yamada3a67e9d2017-01-15 14:59:07 +09002 * Copyright (C) 2011-2014 Panasonic Corporation
3 * Copyright (C) 2015-2016 Socionext Inc.
4 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamadabb2ff9d2014-10-03 19:21:06 +09005 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
Masahiro Yamada663a23f2015-05-29 17:30:00 +09009#include <linux/io.h>
Masahiro Yamadaefdf3402016-01-09 01:51:13 +090010
11#include "../init.h"
12#include "bcu-regs.h"
Masahiro Yamadabb2ff9d2014-10-03 19:21:06 +090013
14#define ch(x) ((x) >= 32 ? 0 : (x) < 0 ? 0x11111111 : 0x11111111 << (x))
15
Masahiro Yamada3a67e9d2017-01-15 14:59:07 +090016void uniphier_ld4_bcu_init(const struct uniphier_board_data *bd)
Masahiro Yamadabb2ff9d2014-10-03 19:21:06 +090017{
18 int shift;
19
20 writel(0x44444444, BCSCR0); /* 0x20000000-0x3fffffff: ASM bus */
21 writel(0x11111111, BCSCR2); /* 0x80000000-0x9fffffff: IPPC/IPPD-bus */
22 writel(0x11111111, BCSCR3); /* 0xa0000000-0xbfffffff: IPPC/IPPD-bus */
23 writel(0x11111111, BCSCR4); /* 0xc0000000-0xdfffffff: IPPC/IPPD-bus */
24 writel(0x11111111, BCSCR5); /* 0xe0000000-0Xffffffff: IPPC/IPPD-bus */
25
26 /* Specify DDR channel */
Masahiro Yamada799e6f22016-02-26 14:21:34 +090027 shift = (bd->dram_ch[1].base - bd->dram_ch[0].base) / 0x04000000 * 4;
Masahiro Yamadabb2ff9d2014-10-03 19:21:06 +090028 writel(ch(shift), BCIPPCCHR2); /* 0x80000000-0x9fffffff */
29
30 shift -= 32;
31 writel(ch(shift), BCIPPCCHR3); /* 0xa0000000-0xbfffffff */
32
33 shift -= 32;
34 writel(ch(shift), BCIPPCCHR4); /* 0xc0000000-0xdfffffff */
Masahiro Yamadabb2ff9d2014-10-03 19:21:06 +090035}