blob: 7c8fec6cbfb754ac53158ff2d08255052b563760 [file] [log] [blame]
Patrick Delaunayddba40a2022-07-05 16:55:57 +02001// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
2/*
3 * Copyright (C) STMicroelectronics 2022 - All Rights Reserved
4 */
5
6/ {
7 aliases {
8 gpio0 = &gpioa;
9 gpio1 = &gpiob;
10 gpio2 = &gpioc;
11 gpio3 = &gpiod;
12 gpio4 = &gpioe;
13 gpio5 = &gpiof;
14 gpio6 = &gpiog;
15 gpio7 = &gpioh;
16 gpio8 = &gpioi;
17 gpio9 = &gpioj;
18 gpio10 = &gpiok;
19 gpio25 = &gpioz;
20 pinctrl0 = &pinctrl;
21 pinctrl1 = &pinctrl_z;
22 };
23
24 binman: binman {
25 multiple-images;
26 };
27
28 soc {
Simon Glassd3a98cb2023-02-13 08:56:33 -070029 bootph-all;
Patrick Delaunayddba40a2022-07-05 16:55:57 +020030
31 ddr: ddr@5a003000 {
Simon Glassd3a98cb2023-02-13 08:56:33 -070032 bootph-all;
Patrick Delaunayddba40a2022-07-05 16:55:57 +020033
34 compatible = "st,stm32mp1-ddr";
35
36 reg = <0x5a003000 0x550
37 0x5a004000 0x234>;
38
39 status = "okay";
40 };
41 };
42
43 /* need PSCI for sysreset during board_f */
44 psci {
Simon Glassd3a98cb2023-02-13 08:56:33 -070045 bootph-some-ram;
Patrick Delaunayddba40a2022-07-05 16:55:57 +020046 };
47};
48
49&bsec {
Simon Glassd3a98cb2023-02-13 08:56:33 -070050 bootph-all;
Patrick Delaunayddba40a2022-07-05 16:55:57 +020051};
52
53&gpioa {
Simon Glassd3a98cb2023-02-13 08:56:33 -070054 bootph-all;
Patrick Delaunayddba40a2022-07-05 16:55:57 +020055};
56
57&gpiob {
Simon Glassd3a98cb2023-02-13 08:56:33 -070058 bootph-all;
Patrick Delaunayddba40a2022-07-05 16:55:57 +020059};
60
61&gpioc {
Simon Glassd3a98cb2023-02-13 08:56:33 -070062 bootph-all;
Patrick Delaunayddba40a2022-07-05 16:55:57 +020063};
64
65&gpiod {
Simon Glassd3a98cb2023-02-13 08:56:33 -070066 bootph-all;
Patrick Delaunayddba40a2022-07-05 16:55:57 +020067};
68
69&gpioe {
Simon Glassd3a98cb2023-02-13 08:56:33 -070070 bootph-all;
Patrick Delaunayddba40a2022-07-05 16:55:57 +020071};
72
73&gpiof {
Simon Glassd3a98cb2023-02-13 08:56:33 -070074 bootph-all;
Patrick Delaunayddba40a2022-07-05 16:55:57 +020075};
76
77&gpiog {
Simon Glassd3a98cb2023-02-13 08:56:33 -070078 bootph-all;
Patrick Delaunayddba40a2022-07-05 16:55:57 +020079};
80
81&gpioh {
Simon Glassd3a98cb2023-02-13 08:56:33 -070082 bootph-all;
Patrick Delaunayddba40a2022-07-05 16:55:57 +020083};
84
85&gpioi {
Simon Glassd3a98cb2023-02-13 08:56:33 -070086 bootph-all;
Patrick Delaunayddba40a2022-07-05 16:55:57 +020087};
88
89&gpioj {
Simon Glassd3a98cb2023-02-13 08:56:33 -070090 bootph-all;
Patrick Delaunayddba40a2022-07-05 16:55:57 +020091};
92
93&gpiok {
Simon Glassd3a98cb2023-02-13 08:56:33 -070094 bootph-all;
Patrick Delaunayddba40a2022-07-05 16:55:57 +020095};
96
97&gpioz {
Simon Glassd3a98cb2023-02-13 08:56:33 -070098 bootph-all;
Patrick Delaunayddba40a2022-07-05 16:55:57 +020099};
100
101&optee {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700102 bootph-some-ram;
Patrick Delaunayddba40a2022-07-05 16:55:57 +0200103};
104
105&iwdg2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700106 bootph-all;
Patrick Delaunayddba40a2022-07-05 16:55:57 +0200107};
108
109/* pre-reloc probe = reserve video frame buffer in video_reserve() */
110&ltdc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700111 bootph-some-ram;
Patrick Delaunayddba40a2022-07-05 16:55:57 +0200112};
113
114/* temp = waiting kernel update */
115&m4_rproc {
116 resets = <&scmi_reset RST_SCMI_MCU>,
117 <&scmi_reset RST_SCMI_MCU_HOLD_BOOT>;
118 reset-names = "mcu_rst", "hold_boot";
119};
120
121&pinctrl {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700122 bootph-all;
Patrick Delaunayddba40a2022-07-05 16:55:57 +0200123};
124
125&pinctrl_z {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700126 bootph-all;
Patrick Delaunayddba40a2022-07-05 16:55:57 +0200127};
128
129&rcc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700130 bootph-all;
Patrick Delaunayddba40a2022-07-05 16:55:57 +0200131};
132
133&scmi {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700134 bootph-some-ram;
Patrick Delaunayddba40a2022-07-05 16:55:57 +0200135};
136
137&usart1 {
138 resets = <&rcc USART1_R>;
139};
140
141&usart2 {
142 resets = <&rcc USART2_R>;
143};
144
145&usart3 {
146 resets = <&rcc USART3_R>;
147};
148
149&uart4 {
150 resets = <&rcc UART4_R>;
151};
152
153&uart5 {
154 resets = <&rcc UART5_R>;
155};
156
157&usart6 {
158 resets = <&rcc USART6_R>;
159};
160
161&uart7 {
162 resets = <&rcc UART7_R>;
163};
164
165&uart8{
166 resets = <&rcc UART8_R>;
167};