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git01.mediatek.com / filogic / uboot / 3a27d4b157baec15f6d3a958b38b76fe77fc9ce6 / . / arch / arm / dts / fsl-lx2160a-rdb.dts
blob: aaa59598bd4c058aeaf88f3ac8ac4657dc3c56f3 [file] [log] [blame]
Priyanka Jainfd45ca02018-11-28 13:04:27 +0000[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+ OR X11
2/*
3 * NXP LX2160ARDB device tree source
4 *
5 * Author: Priyanka Jain <priyanka.jain@nxp.com>
6 * Sriram Dash <sriram.dash@nxp.com>
7 *
Ioana Ciorneic0080632023-03-15 13:04:16 +0200[diff] [blame]8 * Copyright 2018, 2023 NXP
Priyanka Jainfd45ca02018-11-28 13:04:27 +0000[diff] [blame]9 *
10 */
11
12/dts-v1/;
13
14#include "fsl-lx2160a.dtsi"
15
16/ {
17 model = "NXP Layerscape LX2160ARDB Board";
18 compatible = "fsl,lx2160ardb", "fsl,lx2160a";
Kuldeep Singh6b614242019-11-06 16:38:01 +0530[diff] [blame]19 aliases {
20 spi0 = &fspi;
Ioana Ciorneic0080632023-03-15 13:04:16 +0200[diff] [blame]21 serial0 = &uart0;
Kuldeep Singh6b614242019-11-06 16:38:01 +0530[diff] [blame]22 };
Priyanka Jainfd45ca02018-11-28 13:04:27 +0000[diff] [blame]23};
24
Ioana Ciorneibcf6a9d2020-03-18 16:47:44 +0200[diff] [blame]25&dpmac3 {
26 status = "okay";
27 phy-handle = <&aquantia_phy1>;
28 phy-connection-type = "usxgmii";
29};
30
31&dpmac4 {
32 status = "okay";
33 phy-handle = <&aquantia_phy2>;
34 phy-connection-type = "usxgmii";
35};
36
37&dpmac17 {
38 status = "okay";
39 phy-handle = <&rgmii_phy1>;
40 phy-connection-type = "rgmii-id";
41};
42
43&dpmac18 {
44 status = "okay";
45 phy-handle = <&rgmii_phy2>;
46 phy-connection-type = "rgmii-id";
47};
48
49&emdio1 {
50 status = "okay";
51 rgmii_phy1: ethernet-phy@1 {
52 /* AR8035 PHY - "compatible" property not strictly needed */
53 compatible = "ethernet-phy-id004d.d072";
54 reg = <0x1>;
55 /* Poll mode - no "interrupts" property defined */
56 };
57 rgmii_phy2: ethernet-phy@2 {
58 /* AR8035 PHY - "compatible" property not strictly needed */
59 compatible = "ethernet-phy-id004d.d072";
60 reg = <0x2>;
61 /* Poll mode - no "interrupts" property defined */
62 };
63 aquantia_phy1: ethernet-phy@4 {
64 /* AQR107 PHY - "compatible" property not strictly needed */
65 compatible = "ethernet-phy-ieee802.3-c45";
66 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
67 reg = <0x4>;
68 };
69 aquantia_phy2: ethernet-phy@5 {
70 /* AQR107 PHY - "compatible" property not strictly needed */
71 compatible = "ethernet-phy-ieee802.3-c45";
72 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
73 reg = <0x5>;
74 };
75};
76
Priyanka Jainfd45ca02018-11-28 13:04:27 +0000[diff] [blame]77&esdhc0 {
78 status = "okay";
79};
80
81&esdhc1 {
82 status = "okay";
Yinbo Zhud8a7c222019-07-16 15:09:09 +0800[diff] [blame]83 mmc-hs200-1_8v;
Yangbo Lu8b956792020-09-01 16:58:08 +0800[diff] [blame]84 mmc-hs400-1_8v;
85 bus-width = <8>;
Priyanka Jainfd45ca02018-11-28 13:04:27 +0000[diff] [blame]86};
87
Kuldeep Singh6b614242019-11-06 16:38:01 +0530[diff] [blame]88&fspi {
89 status = "okay";
90
91 mt35xu512aba0: flash@0 {
92 #address-cells = <1>;
93 #size-cells = <1>;
94 compatible = "jedec,spi-nor";
95 spi-max-frequency = <50000000>;
96 reg = <0>;
Kuldeep Singh9a3844b2020-03-14 18:23:56 +0530[diff] [blame]97 spi-rx-bus-width = <8>;
98 spi-tx-bus-width = <1>;
Kuldeep Singh6b614242019-11-06 16:38:01 +0530[diff] [blame]99 };
100
101 mt35xu512aba1: flash@1 {
102 #address-cells = <1>;
103 #size-cells = <1>;
104 compatible = "jedec,spi-nor";
105 spi-max-frequency = <50000000>;
106 reg = <1>;
Kuldeep Singh9a3844b2020-03-14 18:23:56 +0530[diff] [blame]107 spi-rx-bus-width = <8>;
108 spi-tx-bus-width = <1>;
Kuldeep Singh6b614242019-11-06 16:38:01 +0530[diff] [blame]109 };
110};
111
Chuanhua Han1a64fb02019-07-10 21:00:26 +0800[diff] [blame]112&i2c0 {
113 status = "okay";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]114 bootph-all;
Chuanhua Han1a64fb02019-07-10 21:00:26 +0800[diff] [blame]115};
116
Chuanhua Han9312dcb2019-07-10 21:00:25 +0800[diff] [blame]117&i2c4 {
118 status = "okay";
119
120 rtc@51 {
Vladimir Oltean20b7d0a2022-01-03 14:47:29 +0200[diff] [blame]121 compatible = "nxp,pcf2129";
Chuanhua Han9312dcb2019-07-10 21:00:25 +0800[diff] [blame]122 reg = <0x51>;
123 };
124};
125
Priyanka Jainfd45ca02018-11-28 13:04:27 +0000[diff] [blame]126&sata0 {
127 status = "okay";
128};
129
130&sata1 {
131 status = "okay";
132};
133
134&sata2 {
135 status = "okay";
136};
137
138&sata3 {
139 status = "okay";
140};
Ioana Ciorneic0080632023-03-15 13:04:16 +0200[diff] [blame]141
142&uart0 {
143 status = "okay";
144};
145
146&uart1 {
147 status = "okay";
148};