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git01.mediatek.com / filogic / uboot / 3a27d4b157baec15f6d3a958b38b76fe77fc9ce6 / . / arch / arm / dts / at91-sama7g5ek-u-boot.dtsi
blob: 8b2e990de727b212c744206cdcc2b0955b48b81c [file] [log] [blame]
Eugen Hristev0de35aa2020-03-10 11:56:38 +0200[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
Eugen Hristevdb55fd62022-03-07 16:29:42 +0200[diff] [blame]3 * at91-sama7g5ek-u-boot.dtsi - Device Tree file for SAMA7G5 SoC u-boot
4 * properties.
Eugen Hristev0de35aa2020-03-10 11:56:38 +0200[diff] [blame]5 *
Eugen Hristevdb55fd62022-03-07 16:29:42 +0200[diff] [blame]6 * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries
Eugen Hristev0de35aa2020-03-10 11:56:38 +0200[diff] [blame]7 *
Eugen Hristevdb55fd62022-03-07 16:29:42 +0200[diff] [blame]8 * Author: Eugen Hristev <eugen.hristev@microchip.com>
9 * Author: Claudiu Beznea <claudiu.beznea@microchip.com>
Eugen Hristev0de35aa2020-03-10 11:56:38 +0200[diff] [blame]10 *
11 */
12
Sergiu Mogafdbed222023-01-04 16:04:16 +0200[diff] [blame]13#include "sama7g5-pinfunc.h"
Sergiu Moga6a0f9402023-01-04 16:04:15 +0200[diff] [blame]14#include <dt-bindings/reset/sama7g5-reset.h>
15#include <dt-bindings/clock/at91.h>
16
Eugen Hristev0de35aa2020-03-10 11:56:38 +0200[diff] [blame]17/ {
18 chosen {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]19 bootph-all;
Eugen Hristev0de35aa2020-03-10 11:56:38 +0200[diff] [blame]20 };
21
Sergiu Moga6a0f9402023-01-04 16:04:15 +0200[diff] [blame]22 utmi {
23 compatible = "simple-bus";
24 #address-cells = <1>;
25 #size-cells = <0>;
26
27 usb_phy0: phy@0 {
28 compatible = "microchip,sama7g5-usb-phy";
29 sfr-phandle = <&sfr>;
30 reg = <0>;
31 clocks = <&utmi_clk USB_UTMI1>;
32 clock-names = "utmi_clk";
33 status = "disabled";
34 #phy-cells = <0>;
35 };
36
37 usb_phy1: phy@1 {
38 compatible = "microchip,sama7g5-usb-phy";
39 sfr-phandle = <&sfr>;
40 reg = <1>;
41 clocks = <&utmi_clk USB_UTMI2>;
42 clock-names = "utmi_clk";
43 status = "disabled";
44 #phy-cells = <0>;
45 };
46
47 usb_phy2: phy@2 {
48 compatible = "microchip,sama7g5-usb-phy";
49 sfr-phandle = <&sfr>;
50 reg = <2>;
51 clocks = <&utmi_clk USB_UTMI3>;
52 clock-names = "utmi_clk";
53 status = "disabled";
54 #phy-cells = <0>;
55 };
56 };
57
58 utmi_clk: utmi-clk {
59 compatible = "microchip,sama7g5-utmi-clk";
60 sfr-phandle = <&sfr>;
61 #clock-cells = <1>;
62 clocks = <&pmc PMC_TYPE_CORE 27>;
63 clock-names = "utmi_clk";
64 resets = <&reset_controller SAMA7G5_RESET_USB_PHY1>,
65 <&reset_controller SAMA7G5_RESET_USB_PHY2>,
66 <&reset_controller SAMA7G5_RESET_USB_PHY3>;
67 reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
68 };
69
Eugen Hristevdb55fd62022-03-07 16:29:42 +0200[diff] [blame]70 soc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]71 bootph-all;
Sergiu Moga6a0f9402023-01-04 16:04:15 +0200[diff] [blame]72
73 usb2: usb@400000 {
74 compatible = "microchip,sama7g5-ohci", "usb-ohci";
75 reg = <0x00400000 0x100000>;
76 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
77 clocks = <&pmc PMC_TYPE_PERIPHERAL 106>, <&utmi_clk USB_UTMI1>, <&usb_clk>;
78 clock-names = "ohci_clk", "hclk", "uhpck";
79 status = "disabled";
80 };
81
82 usb3: usb@500000 {
83 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
84 reg = <0x00500000 0x100000>;
85 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
86 clocks = <&usb_clk>, <&pmc PMC_TYPE_PERIPHERAL 106>;
87 clock-names = "usb_clk", "ehci_clk";
88 status = "disabled";
89 };
90
91 sfr: sfr@e1624000 {
92 compatible = "microchip,sama7g5-sfr", "syscon";
93 reg = <0xe1624000 0x4000>;
94 };
Eugen Hristev0de35aa2020-03-10 11:56:38 +0200[diff] [blame]95 };
96};
97
Claudiu Beznead1092822020-06-02 15:22:21 +0300[diff] [blame]98&main_rc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]99 bootph-all;
Claudiu Beznead1092822020-06-02 15:22:21 +0300[diff] [blame]100};
101
Claudiu Bezneab29850f2020-06-02 15:23:02 +0300[diff] [blame]102&main_xtal {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]103 bootph-all;
Claudiu Bezneab29850f2020-06-02 15:23:02 +0300[diff] [blame]104};
105
Sergiu Mogaf9060c52022-09-01 17:22:40 +0300[diff] [blame]106&pioA {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]107 bootph-all;
Eugen Hristevc06e2fe2020-06-04 10:37:13 +0300[diff] [blame]108};
109
Eugen Hristev83953652020-06-04 10:38:49 +0300[diff] [blame]110&pinctrl_flx3_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]111 bootph-all;
Eugen Hristev83953652020-06-04 10:38:49 +0300[diff] [blame]112};
113
Eugen Hristevdb55fd62022-03-07 16:29:42 +0200[diff] [blame]114&pioA {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]115 bootph-all;
Sergiu Mogafdbed222023-01-04 16:04:16 +0200[diff] [blame]116
117 pinctrl_usb_default: usb_default {
118 pinmux = <PIN_PC6__GPIO>;
119 bias-disable;
120 };
Eugen Hristevdb55fd62022-03-07 16:29:42 +0200[diff] [blame]121};
122
Claudiu Beznea5430a4e2020-06-02 18:42:18 +0300[diff] [blame]123&pit64b0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]124 bootph-all;
Claudiu Beznea5430a4e2020-06-02 18:42:18 +0300[diff] [blame]125};
126
Claudiu Beznea18401a22020-06-02 15:24:25 +0300[diff] [blame]127&pmc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]128 bootph-all;
Claudiu Beznea18401a22020-06-02 15:24:25 +0300[diff] [blame]129};
130
Claudiu Beznead1092822020-06-02 15:22:21 +0300[diff] [blame]131&slow_rc_osc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]132 bootph-all;
Claudiu Beznead1092822020-06-02 15:22:21 +0300[diff] [blame]133};
134
Claudiu Bezneab29850f2020-06-02 15:23:02 +0300[diff] [blame]135&slow_xtal {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]136 bootph-all;
Claudiu Bezneab29850f2020-06-02 15:23:02 +0300[diff] [blame]137};
138
Eugen Hristevdb55fd62022-03-07 16:29:42 +0200[diff] [blame]139&uart3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]140 bootph-all;
Eugen Hristev0de35aa2020-03-10 11:56:38 +0200[diff] [blame]141};
Sergiu Mogafdbed222023-01-04 16:04:16 +0200[diff] [blame]142
143&usb2 {
144 num-ports = <3>;
145 atmel,vbus-gpio = <0
146 0
147 &pioA PIN_PC6 GPIO_ACTIVE_HIGH
148 >;
149 pinctrl-names = "default";
150 pinctrl-0 = <&pinctrl_usb_default>;
151 phys = <&usb_phy2>;
152 phy-names = "usb";
153 status = "okay";
154};
155
156&usb3 {
157 status = "okay";
158};
159
160&usb_phy0 {
161 status = "okay";
162};
163
164&usb_phy1 {
165 status = "okay";
166};
167
168&usb_phy2 {
169 status = "okay";
170};