Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 3a27d4b157baec15f6d3a958b38b76fe77fc9ce6 / . / arch / arm / dts / ast2600-evb.dts
blob: 9aac0e26f280b8daecb1359e72a8072404023c26 [file] [log] [blame]
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2
3/dts-v1/;
4
5#include "ast2600-u-boot.dtsi"
6
7/ {
8 memory {
9 device_type = "memory";
10 reg = <0x80000000 0x40000000>;
11 };
12
13 chosen {
14 stdout-path = &uart5;
15 };
16
17 aliases {
Joel Stanleya0c21182022-06-23 18:35:28 +0930[diff] [blame]18 mmc0 = &emmc;
19 mmc1 = &sdhci0;
20 mmc2 = &sdhci1;
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]21 spi0 = &fmc;
22 spi1 = &spi1;
23 spi2 = &spi2;
24 ethernet0 = &mac0;
25 ethernet1 = &mac1;
26 ethernet2 = &mac2;
27 ethernet3 = &mac3;
28 };
29
30 cpus {
31 cpu@0 {
32 clock-frequency = <800000000>;
33 };
34 cpu@1 {
35 clock-frequency = <800000000>;
36 };
37 };
38};
39
Billy Tsai2193dc62022-03-08 11:04:07 +0800[diff] [blame]40&pwm {
41 status = "okay";
42 pinctrl-names = "default";
43 pinctrl-0 = <&pinctrl_pwm0_default
44 &pinctrl_pwm1_default
45 &pinctrl_pwm2_default
46 &pinctrl_pwm3_default
47 &pinctrl_pwm4_default
48 &pinctrl_pwm5_default
49 &pinctrl_pwm6_default
50 &pinctrl_pwm7_default
51 &pinctrl_pwm8g1_default
52 &pinctrl_pwm9g1_default
53 &pinctrl_pwm10g1_default
54 &pinctrl_pwm11g1_default
55 &pinctrl_pwm12g1_default
56 &pinctrl_pwm13g1_default
57 &pinctrl_pwm14g1_default>;
58};
59
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]60&uart5 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]61 bootph-all;
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]62 status = "okay";
63};
64
65&sdrammc {
66 clock-frequency = <400000000>;
67};
68
69&wdt1 {
70 status = "okay";
71};
72
73&fmc {
74 status = "okay";
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]75 pinctrl-names = "default";
76 pinctrl-0 = <&pinctrl_fmcquad_default>;
77
78 flash@0 {
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]79 status = "okay";
80 spi-max-frequency = <50000000>;
81 spi-tx-bus-width = <4>;
82 spi-rx-bus-width = <4>;
83 };
84
85 flash@1 {
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]86 status = "okay";
87 spi-max-frequency = <50000000>;
88 spi-tx-bus-width = <4>;
89 spi-rx-bus-width = <4>;
90 };
91
92 flash@2 {
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]93 status = "okay";
94 spi-max-frequency = <50000000>;
95 spi-tx-bus-width = <4>;
96 spi-rx-bus-width = <4>;
97 };
98};
99
100&spi1 {
101 status = "okay";
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]102 pinctrl-names = "default";
103 pinctrl-0 = <&pinctrl_spi1_default &pinctrl_spi1abr_default
104 &pinctrl_spi1cs1_default &pinctrl_spi1wp_default
105 &pinctrl_spi1wp_default &pinctrl_spi1quad_default>;
106
107 flash@0 {
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]108 status = "okay";
109 spi-max-frequency = <50000000>;
110 spi-tx-bus-width = <4>;
111 spi-rx-bus-width = <4>;
112 };
113};
114
115&spi2 {
116 status = "okay";
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]117 pinctrl-names = "default";
118 pinctrl-0 = <&pinctrl_spi2_default &pinctrl_spi2cs1_default
119 &pinctrl_spi2cs2_default &pinctrl_spi2quad_default>;
120
121 flash@0 {
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]122 status = "okay";
123 spi-max-frequency = <50000000>;
124 spi-tx-bus-width = <4>;
125 spi-rx-bus-width = <4>;
126 };
127};
128
Joel Stanleya0c21182022-06-23 18:35:28 +0930[diff] [blame]129
130&emmc_controller {
131 status = "okay";
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]132};
133
Joel Stanleya0c21182022-06-23 18:35:28 +0930[diff] [blame]134&emmc {
135 non-removable;
136 bus-width = <4>;
137 max-frequency = <100000000>;
138 clk-phase-mmc-hs200 = <9>, <225>;
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]139};
140
141&i2c4 {
142 status = "okay";
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]143};
144
145&i2c5 {
146 status = "okay";
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]147};
148
149&i2c6 {
150 status = "okay";
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]151};
152
153&i2c7 {
154 status = "okay";
Joel Stanleyadb8d852022-06-23 14:40:36 +0930[diff] [blame]155
156 temp@2e {
157 compatible = "adi,adt7490";
158 reg = <0x2e>;
159 };
160
161 eeprom@50 {
162 compatible = "atmel,24c08";
163 reg = <0x50>;
164 pagesize = <16>;
165 };
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]166};
167
168&i2c8 {
169 status = "okay";
Joel Stanleyadb8d852022-06-23 14:40:36 +0930[diff] [blame]170
171 lm75@4d {
172 compatible = "national,lm75";
173 reg = <0x4d>;
174 };
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]175};
176
Dylan Hung82f25842021-12-09 10:12:26 +0800[diff] [blame]177&mdio0 {
178 status = "okay";
179 #address-cells = <1>;
180 #size-cells = <0>;
181 ethphy0: ethernet-phy@0 {
182 reg = <0>;
183 };
184};
185
186&mdio1 {
187 status = "okay";
188 #address-cells = <1>;
189 #size-cells = <0>;
190 ethphy1: ethernet-phy@0 {
191 reg = <0>;
192 };
193};
194
195&mdio2 {
196 status = "okay";
197 #address-cells = <1>;
198 #size-cells = <0>;
199 ethphy2: ethernet-phy@0 {
200 reg = <0>;
201 };
202};
203
204&mdio3 {
205 status = "okay";
206 #address-cells = <1>;
207 #size-cells = <0>;
208 ethphy3: ethernet-phy@0 {
209 reg = <0>;
210 };
211};
212
213&mac0 {
214 status = "okay";
215 phy-mode = "rgmii-rxid";
216 phy-handle = <&ethphy0>;
217 pinctrl-names = "default";
218 pinctrl-0 = <&pinctrl_rgmii1_default>;
219};
220
221&mac1 {
222 status = "okay";
223 phy-mode = "rgmii-rxid";
224 phy-handle = <&ethphy1>;
225 pinctrl-names = "default";
226 pinctrl-0 = <&pinctrl_rgmii2_default>;
227};
228
229&mac2 {
230 status = "okay";
231 phy-mode = "rgmii";
232 phy-handle = <&ethphy2>;
233 pinctrl-names = "default";
234 pinctrl-0 = <&pinctrl_rgmii3_default>;
235};
236
237&mac3 {
238 status = "okay";
239 phy-mode = "rgmii";
240 phy-handle = <&ethphy3>;
241 pinctrl-names = "default";
242 pinctrl-0 = <&pinctrl_rgmii4_default>;
243};
244
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]245&scu {
246 mac0-clk-delay = <0x1d 0x1c
247 0x10 0x17
248 0x10 0x17>;
249 mac1-clk-delay = <0x1d 0x10
250 0x10 0x10
251 0x10 0x10>;
252 mac2-clk-delay = <0x0a 0x04
253 0x08 0x04
254 0x08 0x04>;
255 mac3-clk-delay = <0x0a 0x04
256 0x08 0x04
257 0x08 0x04>;
258};
Joel Stanleyd18ef4f2021-10-27 14:17:28 +0800[diff] [blame]259
260&hace {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]261 bootph-all;
Joel Stanleyd18ef4f2021-10-27 14:17:28 +0800[diff] [blame]262 status = "okay";
263};
Chia-Wei Wang3435a3f2021-10-27 14:17:31 +0800[diff] [blame]264
265&acry {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]266 bootph-all;
Chia-Wei Wang3435a3f2021-10-27 14:17:31 +0800[diff] [blame]267 status = "okay";
268};