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Kever Yang1a94b9e2017-09-27 16:38:22 +08001/*
2 * (C) Copyright 2017 Rockchip Electronics Co., Ltd
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6#ifndef _ASM_ARCH_SDRAM_RK322X_H
7#define _ASM_ARCH_SDRAM_RK322X_H
8
9#include <common.h>
10
11enum {
12 DDR3 = 3,
13 LPDDR2 = 5,
14 LPDDR3 = 6,
15 UNUSED = 0xFF,
16};
17
18struct rk322x_sdram_channel {
19 /*
20 * bit width in address, eg:
21 * 8 banks using 3 bit to address,
22 * 2 cs using 1 bit to address.
23 */
24 u8 rank;
25 u8 col;
26 u8 bk;
27 u8 bw;
28 u8 dbw;
29 u8 row_3_4;
30 u8 cs0_row;
31 u8 cs1_row;
32#if CONFIG_IS_ENABLED(OF_PLATDATA)
33 /*
34 * For of-platdata, which would otherwise convert this into two
35 * byte-swapped integers. With a size of 9 bytes, this struct will
36 * appear in of-platdata as a byte array.
37 *
38 * If OF_PLATDATA enabled, need to add a dummy byte in dts.(i.e 0xff)
39 */
40 u8 dummy;
41#endif
42};
43
44struct rk322x_ddr_pctl {
45 u32 scfg;
46 u32 sctl;
47 u32 stat;
48 u32 intrstat;
49 u32 reserved0[(0x40 - 0x10) / 4];
50 u32 mcmd;
51 u32 powctl;
52 u32 powstat;
53 u32 cmdtstat;
54 u32 cmdtstaten;
55 u32 reserved1[(0x60 - 0x54) / 4];
56 u32 mrrcfg0;
57 u32 mrrstat0;
58 u32 mrrstat1;
59 u32 reserved2[(0x7c - 0x6c) / 4];
60
61 u32 mcfg1;
62 u32 mcfg;
63 u32 ppcfg;
64 u32 mstat;
65 u32 lpddr2zqcfg;
66 u32 reserved3;
67
68 u32 dtupdes;
69 u32 dtuna;
70 u32 dtune;
71 u32 dtuprd0;
72 u32 dtuprd1;
73 u32 dtuprd2;
74 u32 dtuprd3;
75 u32 dtuawdt;
76 u32 reserved4[(0xc0 - 0xb4) / 4];
77
78 u32 togcnt1u;
79 u32 tinit;
80 u32 trsth;
81 u32 togcnt100n;
82 u32 trefi;
83 u32 tmrd;
84 u32 trfc;
85 u32 trp;
86 u32 trtw;
87 u32 tal;
88 u32 tcl;
89 u32 tcwl;
90 u32 tras;
91 u32 trc;
92 u32 trcd;
93 u32 trrd;
94 u32 trtp;
95 u32 twr;
96 u32 twtr;
97 u32 texsr;
98 u32 txp;
99 u32 txpdll;
100 u32 tzqcs;
101 u32 tzqcsi;
102 u32 tdqs;
103 u32 tcksre;
104 u32 tcksrx;
105 u32 tcke;
106 u32 tmod;
107 u32 trstl;
108 u32 tzqcl;
109 u32 tmrr;
110 u32 tckesr;
111 u32 tdpd;
112 u32 tref_mem_ddr3;
113 u32 reserved5[(0x180 - 0x14c) / 4];
114 u32 ecccfg;
115 u32 ecctst;
116 u32 eccclr;
117 u32 ecclog;
118 u32 reserved6[(0x200 - 0x190) / 4];
119 u32 dtuwactl;
120 u32 dturactl;
121 u32 dtucfg;
122 u32 dtuectl;
123 u32 dtuwd0;
124 u32 dtuwd1;
125 u32 dtuwd2;
126 u32 dtuwd3;
127 u32 dtuwdm;
128 u32 dturd0;
129 u32 dturd1;
130 u32 dturd2;
131 u32 dturd3;
132 u32 dtulfsrwd;
133 u32 dtulfsrrd;
134 u32 dtueaf;
135 /* dfi control registers */
136 u32 dfitctrldelay;
137 u32 dfiodtcfg;
138 u32 dfiodtcfg1;
139 u32 dfiodtrankmap;
140 /* dfi write data registers */
141 u32 dfitphywrdata;
142 u32 dfitphywrlat;
143 u32 reserved7[(0x260 - 0x258) / 4];
144 u32 dfitrddataen;
145 u32 dfitphyrdlat;
146 u32 reserved8[(0x270 - 0x268) / 4];
147 u32 dfitphyupdtype0;
148 u32 dfitphyupdtype1;
149 u32 dfitphyupdtype2;
150 u32 dfitphyupdtype3;
151 u32 dfitctrlupdmin;
152 u32 dfitctrlupdmax;
153 u32 dfitctrlupddly;
154 u32 reserved9;
155 u32 dfiupdcfg;
156 u32 dfitrefmski;
157 u32 dfitctrlupdi;
158 u32 reserved10[(0x2ac - 0x29c) / 4];
159 u32 dfitrcfg0;
160 u32 dfitrstat0;
161 u32 dfitrwrlvlen;
162 u32 dfitrrdlvlen;
163 u32 dfitrrdlvlgateen;
164 u32 dfiststat0;
165 u32 dfistcfg0;
166 u32 dfistcfg1;
167 u32 reserved11;
168 u32 dfitdramclken;
169 u32 dfitdramclkdis;
170 u32 dfistcfg2;
171 u32 dfistparclr;
172 u32 dfistparlog;
173 u32 reserved12[(0x2f0 - 0x2e4) / 4];
174
175 u32 dfilpcfg0;
176 u32 reserved13[(0x300 - 0x2f4) / 4];
177 u32 dfitrwrlvlresp0;
178 u32 dfitrwrlvlresp1;
179 u32 dfitrwrlvlresp2;
180 u32 dfitrrdlvlresp0;
181 u32 dfitrrdlvlresp1;
182 u32 dfitrrdlvlresp2;
183 u32 dfitrwrlvldelay0;
184 u32 dfitrwrlvldelay1;
185 u32 dfitrwrlvldelay2;
186 u32 dfitrrdlvldelay0;
187 u32 dfitrrdlvldelay1;
188 u32 dfitrrdlvldelay2;
189 u32 dfitrrdlvlgatedelay0;
190 u32 dfitrrdlvlgatedelay1;
191 u32 dfitrrdlvlgatedelay2;
192 u32 dfitrcmd;
193 u32 reserved14[(0x3f8 - 0x340) / 4];
194 u32 ipvr;
195 u32 iptr;
196};
197check_member(rk322x_ddr_pctl, iptr, 0x03fc);
198
199struct rk322x_ddr_phy {
200 u32 ddrphy_reg[0x100];
201};
202
203struct rk322x_pctl_timing {
204 u32 togcnt1u;
205 u32 tinit;
206 u32 trsth;
207 u32 togcnt100n;
208 u32 trefi;
209 u32 tmrd;
210 u32 trfc;
211 u32 trp;
212 u32 trtw;
213 u32 tal;
214 u32 tcl;
215 u32 tcwl;
216 u32 tras;
217 u32 trc;
218 u32 trcd;
219 u32 trrd;
220 u32 trtp;
221 u32 twr;
222 u32 twtr;
223 u32 texsr;
224 u32 txp;
225 u32 txpdll;
226 u32 tzqcs;
227 u32 tzqcsi;
228 u32 tdqs;
229 u32 tcksre;
230 u32 tcksrx;
231 u32 tcke;
232 u32 tmod;
233 u32 trstl;
234 u32 tzqcl;
235 u32 tmrr;
236 u32 tckesr;
237 u32 tdpd;
238 u32 trefi_mem_ddr3;
239};
240
241struct rk322x_phy_timing {
242 u32 mr[4];
243 u32 mr11;
244 u32 bl;
245 u32 cl_al;
246};
247
248struct rk322x_msch_timings {
249 u32 ddrtiming;
250 u32 ddrmode;
251 u32 readlatency;
252 u32 activate;
253 u32 devtodev;
254};
255
256struct rk322x_service_sys {
257 u32 id_coreid;
258 u32 id_revisionid;
259 u32 ddrconf;
260 u32 ddrtiming;
261 u32 ddrmode;
262 u32 readlatency;
263 u32 activate;
264 u32 devtodev;
265};
266
267struct rk322x_base_params {
268 struct rk322x_msch_timings noc_timing;
269 u32 ddrconfig;
270 u32 ddr_freq;
271 u32 dramtype;
272 /*
273 * unused for rk322x
274 */
275 u32 stride;
276 u32 odt;
277};
278
279/* PCT_DFISTCFG0 */
280#define DFI_INIT_START BIT(0)
281#define DFI_DATA_BYTE_DISABLE_EN BIT(2)
282
283/* PCT_DFISTCFG1 */
284#define DFI_DRAM_CLK_SR_EN BIT(0)
285#define DFI_DRAM_CLK_DPD_EN BIT(1)
286
287/* PCT_DFISTCFG2 */
288#define DFI_PARITY_INTR_EN BIT(0)
289#define DFI_PARITY_EN BIT(1)
290
291/* PCT_DFILPCFG0 */
292#define TLP_RESP_TIME_SHIFT 16
293#define LP_SR_EN BIT(8)
294#define LP_PD_EN BIT(0)
295
296/* PCT_DFITCTRLDELAY */
297#define TCTRL_DELAY_TIME_SHIFT 0
298
299/* PCT_DFITPHYWRDATA */
300#define TPHY_WRDATA_TIME_SHIFT 0
301
302/* PCT_DFITPHYRDLAT */
303#define TPHY_RDLAT_TIME_SHIFT 0
304
305/* PCT_DFITDRAMCLKDIS */
306#define TDRAM_CLK_DIS_TIME_SHIFT 0
307
308/* PCT_DFITDRAMCLKEN */
309#define TDRAM_CLK_EN_TIME_SHIFT 0
310
311/* PCTL_DFIODTCFG */
312#define RANK0_ODT_WRITE_SEL BIT(3)
313#define RANK1_ODT_WRITE_SEL BIT(11)
314
315/* PCTL_DFIODTCFG1 */
316#define ODT_LEN_BL8_W_SHIFT 16
317
318/* PUBL_ACDLLCR */
319#define ACDLLCR_DLLDIS BIT(31)
320#define ACDLLCR_DLLSRST BIT(30)
321
322/* PUBL_DXDLLCR */
323#define DXDLLCR_DLLDIS BIT(31)
324#define DXDLLCR_DLLSRST BIT(30)
325
326/* PUBL_DLLGCR */
327#define DLLGCR_SBIAS BIT(30)
328
329/* PUBL_DXGCR */
330#define DQSRTT BIT(9)
331#define DQRTT BIT(10)
332
333/* PIR */
334#define PIR_INIT BIT(0)
335#define PIR_DLLSRST BIT(1)
336#define PIR_DLLLOCK BIT(2)
337#define PIR_ZCAL BIT(3)
338#define PIR_ITMSRST BIT(4)
339#define PIR_DRAMRST BIT(5)
340#define PIR_DRAMINIT BIT(6)
341#define PIR_QSTRN BIT(7)
342#define PIR_RVTRN BIT(8)
343#define PIR_ICPC BIT(16)
344#define PIR_DLLBYP BIT(17)
345#define PIR_CTLDINIT BIT(18)
346#define PIR_CLRSR BIT(28)
347#define PIR_LOCKBYP BIT(29)
348#define PIR_ZCALBYP BIT(30)
349#define PIR_INITBYP BIT(31)
350
351/* PGCR */
352#define PGCR_DFTLMT_SHIFT 3
353#define PGCR_DFTCMP_SHIFT 2
354#define PGCR_DQSCFG_SHIFT 1
355#define PGCR_ITMDMD_SHIFT 0
356
357/* PGSR */
358#define PGSR_IDONE BIT(0)
359#define PGSR_DLDONE BIT(1)
360#define PGSR_ZCDONE BIT(2)
361#define PGSR_DIDONE BIT(3)
362#define PGSR_DTDONE BIT(4)
363#define PGSR_DTERR BIT(5)
364#define PGSR_DTIERR BIT(6)
365#define PGSR_DFTERR BIT(7)
366#define PGSR_RVERR BIT(8)
367#define PGSR_RVEIRR BIT(9)
368
369/* PTR0 */
370#define PRT_ITMSRST_SHIFT 18
371#define PRT_DLLLOCK_SHIFT 6
372#define PRT_DLLSRST_SHIFT 0
373
374/* PTR1 */
375#define PRT_DINIT0_SHIFT 0
376#define PRT_DINIT1_SHIFT 19
377
378/* PTR2 */
379#define PRT_DINIT2_SHIFT 0
380#define PRT_DINIT3_SHIFT 17
381
382/* DCR */
383#define DDRMD_LPDDR 0
384#define DDRMD_DDR 1
385#define DDRMD_DDR2 2
386#define DDRMD_DDR3 3
387#define DDRMD_LPDDR2_LPDDR3 4
388#define DDRMD_MASK 7
389#define DDRMD_SHIFT 0
390#define PDQ_MASK 7
391#define PDQ_SHIFT 4
392
393/* DXCCR */
394#define DQSNRES_MASK 0xf
395#define DQSNRES_SHIFT 8
396#define DQSRES_MASK 0xf
397#define DQSRES_SHIFT 4
398
399/* DTPR */
400#define TDQSCKMAX_SHIFT 27
401#define TDQSCKMAX_MASK 7
402#define TDQSCK_SHIFT 24
403#define TDQSCK_MASK 7
404
405/* DSGCR */
406#define DQSGX_SHIFT 5
407#define DQSGX_MASK 7
408#define DQSGE_SHIFT 8
409#define DQSGE_MASK 7
410
411/* SCTL */
412#define INIT_STATE 0
413#define CFG_STATE 1
414#define GO_STATE 2
415#define SLEEP_STATE 3
416#define WAKEUP_STATE 4
417
418/* STAT */
419#define LP_TRIG_SHIFT 4
420#define LP_TRIG_MASK 7
421#define PCTL_STAT_MASK 7
422#define INIT_MEM 0
423#define CONFIG 1
424#define CONFIG_REQ 2
425#define ACCESS 3
426#define ACCESS_REQ 4
427#define LOW_POWER 5
428#define LOW_POWER_ENTRY_REQ 6
429#define LOW_POWER_EXIT_REQ 7
430
431/* ZQCR*/
432#define PD_OUTPUT_SHIFT 0
433#define PU_OUTPUT_SHIFT 5
434#define PD_ONDIE_SHIFT 10
435#define PU_ONDIE_SHIFT 15
436#define ZDEN_SHIFT 28
437
438/* DDLGCR */
439#define SBIAS_BYPASS BIT(23)
440
441/* MCFG */
442#define MDDR_LPDDR2_CLK_STOP_IDLE_SHIFT 24
443#define PD_IDLE_SHIFT 8
444#define MDDR_EN (2 << 22)
445#define LPDDR2_EN (3 << 22)
446#define LPDDR3_EN (1 << 22)
447#define DDR2_EN (0 << 5)
448#define DDR3_EN (1 << 5)
449#define LPDDR2_S2 (0 << 6)
450#define LPDDR2_S4 (1 << 6)
451#define MDDR_LPDDR2_BL_2 (0 << 20)
452#define MDDR_LPDDR2_BL_4 (1 << 20)
453#define MDDR_LPDDR2_BL_8 (2 << 20)
454#define MDDR_LPDDR2_BL_16 (3 << 20)
455#define DDR2_DDR3_BL_4 0
456#define DDR2_DDR3_BL_8 1
457#define TFAW_SHIFT 18
458#define PD_EXIT_SLOW (0 << 17)
459#define PD_EXIT_FAST (1 << 17)
460#define PD_TYPE_SHIFT 16
461#define BURSTLENGTH_SHIFT 20
462
463/* POWCTL */
464#define POWER_UP_START BIT(0)
465
466/* POWSTAT */
467#define POWER_UP_DONE BIT(0)
468
469/* MCMD */
470enum {
471 DESELECT_CMD = 0,
472 PREA_CMD,
473 REF_CMD,
474 MRS_CMD,
475 ZQCS_CMD,
476 ZQCL_CMD,
477 RSTL_CMD,
478 MRR_CMD = 8,
479 DPDE_CMD,
480};
481
482#define BANK_ADDR_MASK 7
483#define BANK_ADDR_SHIFT 17
484#define CMD_ADDR_MASK 0x1fff
485#define CMD_ADDR_SHIFT 4
486
487#define LPDDR23_MA_SHIFT 4
488#define LPDDR23_MA_MASK 0xff
489#define LPDDR23_OP_SHIFT 12
490#define LPDDR23_OP_MASK 0xff
491
492#define START_CMD (1u << 31)
493
494/* DDRPHY REG */
495enum {
496 /* DDRPHY_REG0 */
497 SOFT_RESET_MASK = 3,
498 SOFT_DERESET_ANALOG = 1 << 2,
499 SOFT_DERESET_DIGITAL = 1 << 3,
500 SOFT_RESET_SHIFT = 2,
501
502 /* DDRPHY REG1 */
503 PHY_DDR3 = 0,
504 PHY_DDR2 = 1,
505 PHY_LPDDR3 = 2,
506 PHY_LPDDR2 = 3,
507
508 PHT_BL_8 = 1 << 2,
509 PHY_BL_4 = 0 << 2,
510
511 /* DDRPHY_REG2 */
512 MEMORY_SELECT_DDR3 = 0 << 0,
513 MEMORY_SELECT_LPDDR3 = 2 << 0,
514 MEMORY_SELECT_LPDDR2 = 3 << 0,
515 DQS_SQU_CAL_SEL_CS0_CS1 = 0 << 4,
516 DQS_SQU_CAL_SEL_CS1 = 1 << 4,
517 DQS_SQU_CAL_SEL_CS0 = 2 << 4,
518 DQS_SQU_CAL_NORMAL_MODE = 0 << 1,
519 DQS_SQU_CAL_BYPASS_MODE = 1 << 1,
520 DQS_SQU_CAL_START = 1 << 0,
521 DQS_SQU_NO_CAL = 0 << 0,
522};
523
524/* CK pull up/down driver strength control */
525enum {
526 PHY_RON_RTT_DISABLE = 0,
527 PHY_RON_RTT_451OHM = 1,
528 PHY_RON_RTT_225OHM,
529 PHY_RON_RTT_150OHM,
530 PHY_RON_RTT_112OHM,
531 PHY_RON_RTT_90OHM,
532 PHY_RON_RTT_75OHM,
533 PHY_RON_RTT_64OHM = 7,
534
535 PHY_RON_RTT_56OHM = 16,
536 PHY_RON_RTT_50OHM,
537 PHY_RON_RTT_45OHM,
538 PHY_RON_RTT_41OHM,
539 PHY_RON_RTT_37OHM,
540 PHY_RON_RTT_34OHM,
541 PHY_RON_RTT_33OHM,
542 PHY_RON_RTT_30OHM = 23,
543
544 PHY_RON_RTT_28OHM = 24,
545 PHY_RON_RTT_26OHM,
546 PHY_RON_RTT_25OHM,
547 PHY_RON_RTT_23OHM,
548 PHY_RON_RTT_22OHM,
549 PHY_RON_RTT_21OHM,
550 PHY_RON_RTT_20OHM,
551 PHY_RON_RTT_19OHM = 31,
552};
553
554/* DQS squelch DLL delay */
555enum {
556 DQS_DLL_NO_DELAY = 0,
557 DQS_DLL_22P5_DELAY,
558 DQS_DLL_45_DELAY,
559 DQS_DLL_67P5_DELAY,
560 DQS_DLL_90_DELAY,
561 DQS_DLL_112P5_DELAY,
562 DQS_DLL_135_DELAY,
563 DQS_DLL_157P5_DELAY,
564};
565
566/* GRF_SOC_CON0 */
567#define GRF_DDR_16BIT_EN (((0x1 << 0) << 16) | (0x1 << 0))
568#define GRF_DDR_32BIT_EN (((0x1 << 0) << 16) | (0x0 << 0))
569#define GRF_MSCH_NOC_16BIT_EN (((0x1 << 7) << 16) | (0x1 << 7))
570#define GRF_MSCH_NOC_32BIT_EN (((0x1 << 7) << 16) | (0x0 << 7))
571
572#define GRF_DDRPHY_BUFFEREN_CORE_EN (((0x1 << 8) << 16) | (0x0 << 8))
573#define GRF_DDRPHY_BUFFEREN_CORE_DIS (((0x1 << 8) << 16) | (0x1 << 8))
574
575#define GRF_DDR3_EN (((0x1 << 6) << 16) | (0x1 << 6))
576#define GRF_LPDDR2_3_EN (((0x1 << 6) << 16) | (0x0 << 6))
577
578#define PHY_DRV_ODT_SET(n) (((n) << 4) | (n))
579#define DDR3_DLL_RESET (1 << 8)
580
581#endif /* _ASM_ARCH_SDRAM_RK322X_H */