Michal Simek | 89f0674 | 2008-03-28 12:42:29 +0100 | [diff] [blame] | 1 | /****************************************************************************** |
| 2 | * |
| 3 | * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" |
| 4 | * AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND |
| 5 | * SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, |
| 6 | * OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, |
| 7 | * APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION |
| 8 | * THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, |
| 9 | * AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE |
| 10 | * FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY |
| 11 | * WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE |
| 12 | * IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR |
| 13 | * REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF |
| 14 | * INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS |
| 15 | * FOR A PARTICULAR PURPOSE. |
| 16 | * |
| 17 | * (C) Copyright 2007-2008 Michal Simek |
| 18 | * Michal SIMEK <monstr@monstr.eu> |
| 19 | * |
| 20 | * (c) Copyright 2003 Xilinx Inc. |
| 21 | * All rights reserved. |
| 22 | * |
| 23 | ******************************************************************************/ |
| 24 | |
| 25 | #include <config.h> |
| 26 | #include <common.h> |
| 27 | #include <net.h> |
| 28 | #include <asm/io.h> |
| 29 | |
| 30 | #include <asm/asm.h> |
| 31 | |
| 32 | #undef DEBUG |
| 33 | |
| 34 | typedef struct { |
| 35 | u32 regbaseaddress; /* Base address of registers */ |
| 36 | u32 databaseaddress; /* Base address of data for FIFOs */ |
| 37 | } xpacketfifov100b; |
| 38 | |
| 39 | typedef struct { |
| 40 | u32 baseaddress; /* Base address (of IPIF) */ |
| 41 | u32 isstarted; /* Device is currently started 0-no, 1-yes */ |
| 42 | xpacketfifov100b recvfifo; /* FIFO used to receive frames */ |
| 43 | xpacketfifov100b sendfifo; /* FIFO used to send frames */ |
| 44 | } xemac; |
| 45 | |
| 46 | #define XIIF_V123B_IISR_OFFSET 32UL /* IP interrupt status register */ |
| 47 | #define XIIF_V123B_RESET_MASK 0xAUL |
| 48 | #define XIIF_V123B_RESETR_OFFSET 64UL /* reset register */ |
| 49 | |
| 50 | /* This constant is used with the Reset Register */ |
| 51 | #define XPF_RESET_FIFO_MASK 0x0000000A |
| 52 | #define XPF_COUNT_STATUS_REG_OFFSET 4UL |
| 53 | |
| 54 | /* These constants are used with the Occupancy/Vacancy Count Register. This |
| 55 | * register also contains FIFO status */ |
| 56 | #define XPF_COUNT_MASK 0x0000FFFF |
| 57 | #define XPF_DEADLOCK_MASK 0x20000000 |
| 58 | |
| 59 | /* Offset of the MAC registers from the IPIF base address */ |
| 60 | #define XEM_REG_OFFSET 0x1100UL |
| 61 | |
| 62 | /* |
| 63 | * Register offsets for the Ethernet MAC. Each register is 32 bits. |
| 64 | */ |
| 65 | #define XEM_ECR_OFFSET (XEM_REG_OFFSET + 0x4) /* MAC Control */ |
| 66 | #define XEM_SAH_OFFSET (XEM_REG_OFFSET + 0xC) /* Station addr, high */ |
| 67 | #define XEM_SAL_OFFSET (XEM_REG_OFFSET + 0x10) /* Station addr, low */ |
| 68 | #define XEM_RPLR_OFFSET (XEM_REG_OFFSET + 0x1C) /* Rx packet length */ |
| 69 | #define XEM_TPLR_OFFSET (XEM_REG_OFFSET + 0x20) /* Tx packet length */ |
| 70 | #define XEM_TSR_OFFSET (XEM_REG_OFFSET + 0x24) /* Tx status */ |
| 71 | |
| 72 | #define XEM_PFIFO_OFFSET 0x2000UL |
| 73 | /* Tx registers */ |
| 74 | #define XEM_PFIFO_TXREG_OFFSET (XEM_PFIFO_OFFSET + 0x0) |
| 75 | /* Rx registers */ |
| 76 | #define XEM_PFIFO_RXREG_OFFSET (XEM_PFIFO_OFFSET + 0x10) |
| 77 | /* Tx keyhole */ |
| 78 | #define XEM_PFIFO_TXDATA_OFFSET (XEM_PFIFO_OFFSET + 0x100) |
| 79 | /* Rx keyhole */ |
| 80 | #define XEM_PFIFO_RXDATA_OFFSET (XEM_PFIFO_OFFSET + 0x200) |
| 81 | |
| 82 | /* |
| 83 | * EMAC Interrupt Registers (Status and Enable) masks. These registers are |
| 84 | * part of the IPIF IP Interrupt registers |
| 85 | */ |
| 86 | /* A mask for all transmit interrupts, used in polled mode */ |
| 87 | #define XEM_EIR_XMIT_ALL_MASK (XEM_EIR_XMIT_DONE_MASK |\ |
| 88 | XEM_EIR_XMIT_ERROR_MASK | \ |
| 89 | XEM_EIR_XMIT_SFIFO_EMPTY_MASK |\ |
| 90 | XEM_EIR_XMIT_LFIFO_FULL_MASK) |
| 91 | |
| 92 | /* Xmit complete */ |
| 93 | #define XEM_EIR_XMIT_DONE_MASK 0x00000001UL |
| 94 | /* Recv complete */ |
| 95 | #define XEM_EIR_RECV_DONE_MASK 0x00000002UL |
| 96 | /* Xmit error */ |
| 97 | #define XEM_EIR_XMIT_ERROR_MASK 0x00000004UL |
| 98 | /* Recv error */ |
| 99 | #define XEM_EIR_RECV_ERROR_MASK 0x00000008UL |
| 100 | /* Xmit status fifo empty */ |
| 101 | #define XEM_EIR_XMIT_SFIFO_EMPTY_MASK 0x00000010UL |
| 102 | /* Recv length fifo empty */ |
| 103 | #define XEM_EIR_RECV_LFIFO_EMPTY_MASK 0x00000020UL |
| 104 | /* Xmit length fifo full */ |
| 105 | #define XEM_EIR_XMIT_LFIFO_FULL_MASK 0x00000040UL |
| 106 | /* Recv length fifo overrun */ |
| 107 | #define XEM_EIR_RECV_LFIFO_OVER_MASK 0x00000080UL |
| 108 | /* Recv length fifo underrun */ |
| 109 | #define XEM_EIR_RECV_LFIFO_UNDER_MASK 0x00000100UL |
| 110 | /* Xmit status fifo overrun */ |
| 111 | #define XEM_EIR_XMIT_SFIFO_OVER_MASK 0x00000200UL |
| 112 | /* Transmit status fifo underrun */ |
| 113 | #define XEM_EIR_XMIT_SFIFO_UNDER_MASK 0x00000400UL |
| 114 | /* Transmit length fifo overrun */ |
| 115 | #define XEM_EIR_XMIT_LFIFO_OVER_MASK 0x00000800UL |
| 116 | /* Transmit length fifo underrun */ |
| 117 | #define XEM_EIR_XMIT_LFIFO_UNDER_MASK 0x00001000UL |
| 118 | /* Transmit pause pkt received */ |
| 119 | #define XEM_EIR_XMIT_PAUSE_MASK 0x00002000UL |
| 120 | |
| 121 | /* |
| 122 | * EMAC Control Register (ECR) |
| 123 | */ |
| 124 | /* Full duplex mode */ |
| 125 | #define XEM_ECR_FULL_DUPLEX_MASK 0x80000000UL |
| 126 | /* Reset transmitter */ |
| 127 | #define XEM_ECR_XMIT_RESET_MASK 0x40000000UL |
| 128 | /* Enable transmitter */ |
| 129 | #define XEM_ECR_XMIT_ENABLE_MASK 0x20000000UL |
| 130 | /* Reset receiver */ |
| 131 | #define XEM_ECR_RECV_RESET_MASK 0x10000000UL |
| 132 | /* Enable receiver */ |
| 133 | #define XEM_ECR_RECV_ENABLE_MASK 0x08000000UL |
| 134 | /* Enable PHY */ |
| 135 | #define XEM_ECR_PHY_ENABLE_MASK 0x04000000UL |
| 136 | /* Enable xmit pad insert */ |
| 137 | #define XEM_ECR_XMIT_PAD_ENABLE_MASK 0x02000000UL |
| 138 | /* Enable xmit FCS insert */ |
| 139 | #define XEM_ECR_XMIT_FCS_ENABLE_MASK 0x01000000UL |
| 140 | /* Enable unicast addr */ |
| 141 | #define XEM_ECR_UNICAST_ENABLE_MASK 0x00020000UL |
| 142 | /* Enable broadcast addr */ |
| 143 | #define XEM_ECR_BROAD_ENABLE_MASK 0x00008000UL |
| 144 | |
| 145 | /* |
| 146 | * Transmit Status Register (TSR) |
| 147 | */ |
| 148 | /* Transmit excess deferral */ |
| 149 | #define XEM_TSR_EXCESS_DEFERRAL_MASK 0x80000000UL |
| 150 | /* Transmit late collision */ |
| 151 | #define XEM_TSR_LATE_COLLISION_MASK 0x01000000UL |
| 152 | |
| 153 | #define ENET_MAX_MTU PKTSIZE |
| 154 | #define ENET_ADDR_LENGTH 6 |
| 155 | |
| 156 | static unsigned int etherrxbuff[PKTSIZE_ALIGN/4]; /* Receive buffer */ |
| 157 | |
| 158 | static u8 emacaddr[ENET_ADDR_LENGTH] = { 0x00, 0x0a, 0x35, 0x00, 0x22, 0x01 }; |
| 159 | |
| 160 | static xemac emac; |
| 161 | |
| 162 | void eth_halt(void) |
| 163 | { |
| 164 | debug ("eth_halt\n"); |
| 165 | } |
| 166 | |
| 167 | int eth_init(bd_t * bis) |
| 168 | { |
Mike Frysinger | b203965 | 2009-02-11 19:01:26 -0500 | [diff] [blame] | 169 | uchar enetaddr[6]; |
Michal Simek | 89f0674 | 2008-03-28 12:42:29 +0100 | [diff] [blame] | 170 | u32 helpreg; |
| 171 | debug ("EMAC Initialization Started\n\r"); |
| 172 | |
| 173 | if (emac.isstarted) { |
| 174 | puts("Emac is started\n"); |
| 175 | return 0; |
| 176 | } |
| 177 | |
| 178 | memset (&emac, 0, sizeof (xemac)); |
| 179 | |
| 180 | emac.baseaddress = XILINX_EMAC_BASEADDR; |
| 181 | |
| 182 | /* Setting up FIFOs */ |
| 183 | emac.recvfifo.regbaseaddress = emac.baseaddress + |
| 184 | XEM_PFIFO_RXREG_OFFSET; |
| 185 | emac.recvfifo.databaseaddress = emac.baseaddress + |
| 186 | XEM_PFIFO_RXDATA_OFFSET; |
| 187 | out_be32 (emac.recvfifo.regbaseaddress, XPF_RESET_FIFO_MASK); |
| 188 | |
| 189 | emac.sendfifo.regbaseaddress = emac.baseaddress + |
| 190 | XEM_PFIFO_TXREG_OFFSET; |
| 191 | emac.sendfifo.databaseaddress = emac.baseaddress + |
| 192 | XEM_PFIFO_TXDATA_OFFSET; |
| 193 | out_be32 (emac.sendfifo.regbaseaddress, XPF_RESET_FIFO_MASK); |
| 194 | |
| 195 | /* Reset the entire IPIF */ |
| 196 | out_be32 (emac.baseaddress + XIIF_V123B_RESETR_OFFSET, |
| 197 | XIIF_V123B_RESET_MASK); |
| 198 | |
| 199 | /* Stopping EMAC for setting up MAC */ |
| 200 | helpreg = in_be32 (emac.baseaddress + XEM_ECR_OFFSET); |
| 201 | helpreg &= ~(XEM_ECR_XMIT_ENABLE_MASK | XEM_ECR_RECV_ENABLE_MASK); |
| 202 | out_be32 (emac.baseaddress + XEM_ECR_OFFSET, helpreg); |
| 203 | |
Mike Frysinger | b203965 | 2009-02-11 19:01:26 -0500 | [diff] [blame] | 204 | if (!eth_getenv_enetaddr("ethaddr", enetaddr)) { |
| 205 | memcpy(enetaddr, emacaddr, ENET_ADDR_LENGTH); |
| 206 | eth_setenv_enetaddr("ethaddr", enetaddr); |
Michal Simek | 89f0674 | 2008-03-28 12:42:29 +0100 | [diff] [blame] | 207 | } |
| 208 | |
| 209 | /* Set the device station address high and low registers */ |
Mike Frysinger | b203965 | 2009-02-11 19:01:26 -0500 | [diff] [blame] | 210 | helpreg = (enetaddr[0] << 8) | enetaddr[1]; |
Michal Simek | 89f0674 | 2008-03-28 12:42:29 +0100 | [diff] [blame] | 211 | out_be32 (emac.baseaddress + XEM_SAH_OFFSET, helpreg); |
Mike Frysinger | b203965 | 2009-02-11 19:01:26 -0500 | [diff] [blame] | 212 | helpreg = (enetaddr[2] << 24) | (enetaddr[3] << 16) | |
| 213 | (enetaddr[4] << 8) | enetaddr[5]; |
Michal Simek | 89f0674 | 2008-03-28 12:42:29 +0100 | [diff] [blame] | 214 | out_be32 (emac.baseaddress + XEM_SAL_OFFSET, helpreg); |
| 215 | |
| 216 | helpreg = XEM_ECR_UNICAST_ENABLE_MASK | XEM_ECR_BROAD_ENABLE_MASK | |
| 217 | XEM_ECR_FULL_DUPLEX_MASK | XEM_ECR_XMIT_FCS_ENABLE_MASK | |
| 218 | XEM_ECR_XMIT_PAD_ENABLE_MASK | XEM_ECR_PHY_ENABLE_MASK; |
| 219 | out_be32 (emac.baseaddress + XEM_ECR_OFFSET, helpreg); |
| 220 | |
| 221 | emac.isstarted = 1; |
| 222 | |
| 223 | /* Enable the transmitter, and receiver */ |
| 224 | helpreg = in_be32 (emac.baseaddress + XEM_ECR_OFFSET); |
| 225 | helpreg &= ~(XEM_ECR_XMIT_RESET_MASK | XEM_ECR_RECV_RESET_MASK); |
| 226 | helpreg |= (XEM_ECR_XMIT_ENABLE_MASK | XEM_ECR_RECV_ENABLE_MASK); |
| 227 | out_be32 (emac.baseaddress + XEM_ECR_OFFSET, helpreg); |
| 228 | |
| 229 | printf("EMAC Initialization complete\n\r"); |
| 230 | return 0; |
| 231 | } |
| 232 | |
| 233 | int eth_send(volatile void *ptr, int len) |
| 234 | { |
| 235 | u32 intrstatus; |
| 236 | u32 xmitstatus; |
| 237 | u32 fifocount; |
| 238 | u32 wordcount; |
| 239 | u32 extrabytecount; |
| 240 | u32 *wordbuffer = (u32 *) ptr; |
| 241 | |
| 242 | if (len > ENET_MAX_MTU) |
| 243 | len = ENET_MAX_MTU; |
| 244 | |
| 245 | /* |
| 246 | * Check for overruns and underruns for the transmit status and length |
| 247 | * FIFOs and make sure the send packet FIFO is not deadlocked. |
| 248 | * Any of these conditions is bad enough that we do not want to |
| 249 | * continue. The upper layer software should reset the device to resolve |
| 250 | * the error. |
| 251 | */ |
| 252 | intrstatus = in_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET); |
| 253 | if (intrstatus & (XEM_EIR_XMIT_SFIFO_OVER_MASK | |
| 254 | XEM_EIR_XMIT_LFIFO_OVER_MASK)) { |
| 255 | debug ("Transmitting overrun error\n"); |
| 256 | return 0; |
| 257 | } else if (intrstatus & (XEM_EIR_XMIT_SFIFO_UNDER_MASK | |
| 258 | XEM_EIR_XMIT_LFIFO_UNDER_MASK)) { |
| 259 | debug ("Transmitting underrun error\n"); |
| 260 | return 0; |
| 261 | } else if (in_be32 (emac.sendfifo.regbaseaddress + |
| 262 | XPF_COUNT_STATUS_REG_OFFSET) & XPF_DEADLOCK_MASK) { |
| 263 | debug ("Transmitting fifo error\n"); |
| 264 | return 0; |
| 265 | } |
| 266 | |
| 267 | /* |
| 268 | * Before writing to the data FIFO, make sure the length FIFO is not |
| 269 | * full. The data FIFO might not be full yet even though the length FIFO |
| 270 | * is. This avoids an overrun condition on the length FIFO and keeps the |
| 271 | * FIFOs in sync. |
| 272 | * |
| 273 | * Clear the latched LFIFO_FULL bit so next time around the most |
| 274 | * current status is represented |
| 275 | */ |
| 276 | if (intrstatus & XEM_EIR_XMIT_LFIFO_FULL_MASK) { |
| 277 | out_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET, |
| 278 | intrstatus & XEM_EIR_XMIT_LFIFO_FULL_MASK); |
| 279 | debug ("Fifo is full\n"); |
| 280 | return 0; |
| 281 | } |
| 282 | |
| 283 | /* get the count of how many words may be inserted into the FIFO */ |
| 284 | fifocount = in_be32 (emac.sendfifo.regbaseaddress + |
| 285 | XPF_COUNT_STATUS_REG_OFFSET) & XPF_COUNT_MASK; |
| 286 | wordcount = len >> 2; |
| 287 | extrabytecount = len & 0x3; |
| 288 | |
| 289 | if (fifocount < wordcount) { |
| 290 | debug ("Sending packet is larger then size of FIFO\n"); |
| 291 | return 0; |
| 292 | } |
| 293 | |
| 294 | for (fifocount = 0; fifocount < wordcount; fifocount++) { |
| 295 | out_be32 (emac.sendfifo.databaseaddress, wordbuffer[fifocount]); |
| 296 | } |
| 297 | if (extrabytecount > 0) { |
| 298 | u32 lastword = 0; |
| 299 | u8 *extrabytesbuffer = (u8 *) (wordbuffer + wordcount); |
| 300 | |
| 301 | if (extrabytecount == 1) { |
| 302 | lastword = extrabytesbuffer[0] << 24; |
| 303 | } else if (extrabytecount == 2) { |
| 304 | lastword = extrabytesbuffer[0] << 24 | |
| 305 | extrabytesbuffer[1] << 16; |
| 306 | } else if (extrabytecount == 3) { |
| 307 | lastword = extrabytesbuffer[0] << 24 | |
| 308 | extrabytesbuffer[1] << 16 | |
| 309 | extrabytesbuffer[2] << 8; |
| 310 | } |
| 311 | out_be32 (emac.sendfifo.databaseaddress, lastword); |
| 312 | } |
| 313 | |
| 314 | /* Loop on the MAC's status to wait for any pause to complete */ |
| 315 | intrstatus = in_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET); |
| 316 | while ((intrstatus & XEM_EIR_XMIT_PAUSE_MASK) != 0) { |
| 317 | intrstatus = in_be32 ((emac.baseaddress) + |
| 318 | XIIF_V123B_IISR_OFFSET); |
| 319 | /* Clear the pause status from the transmit status register */ |
| 320 | out_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET, |
| 321 | intrstatus & XEM_EIR_XMIT_PAUSE_MASK); |
| 322 | } |
| 323 | |
| 324 | /* |
| 325 | * Set the MAC's transmit packet length register to tell it to transmit |
| 326 | */ |
| 327 | out_be32 (emac.baseaddress + XEM_TPLR_OFFSET, len); |
| 328 | |
| 329 | /* |
| 330 | * Loop on the MAC's status to wait for the transmit to complete. |
| 331 | * The transmit status is in the FIFO when the XMIT_DONE bit is set. |
| 332 | */ |
| 333 | do { |
| 334 | intrstatus = in_be32 ((emac.baseaddress) + |
| 335 | XIIF_V123B_IISR_OFFSET); |
| 336 | } |
| 337 | while ((intrstatus & XEM_EIR_XMIT_DONE_MASK) == 0); |
| 338 | |
| 339 | xmitstatus = in_be32 (emac.baseaddress + XEM_TSR_OFFSET); |
| 340 | |
| 341 | if (intrstatus & (XEM_EIR_XMIT_SFIFO_OVER_MASK | |
| 342 | XEM_EIR_XMIT_LFIFO_OVER_MASK)) { |
| 343 | debug ("Transmitting overrun error\n"); |
| 344 | return 0; |
| 345 | } else if (intrstatus & (XEM_EIR_XMIT_SFIFO_UNDER_MASK | |
| 346 | XEM_EIR_XMIT_LFIFO_UNDER_MASK)) { |
| 347 | debug ("Transmitting underrun error\n"); |
| 348 | return 0; |
| 349 | } |
| 350 | |
| 351 | /* Clear the interrupt status register of transmit statuses */ |
| 352 | out_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET, |
| 353 | intrstatus & XEM_EIR_XMIT_ALL_MASK); |
| 354 | |
| 355 | /* |
| 356 | * Collision errors are stored in the transmit status register |
| 357 | * instead of the interrupt status register |
| 358 | */ |
| 359 | if ((xmitstatus & XEM_TSR_EXCESS_DEFERRAL_MASK) || |
| 360 | (xmitstatus & XEM_TSR_LATE_COLLISION_MASK)) { |
| 361 | debug ("Transmitting collision error\n"); |
| 362 | return 0; |
| 363 | } |
| 364 | return 1; |
| 365 | } |
| 366 | |
| 367 | int eth_rx(void) |
| 368 | { |
| 369 | u32 pktlength; |
| 370 | u32 intrstatus; |
| 371 | u32 fifocount; |
| 372 | u32 wordcount; |
| 373 | u32 extrabytecount; |
| 374 | u32 lastword; |
| 375 | u8 *extrabytesbuffer; |
| 376 | |
| 377 | if (in_be32 (emac.recvfifo.regbaseaddress + XPF_COUNT_STATUS_REG_OFFSET) |
| 378 | & XPF_DEADLOCK_MASK) { |
| 379 | out_be32 (emac.recvfifo.regbaseaddress, XPF_RESET_FIFO_MASK); |
| 380 | debug ("Receiving FIFO deadlock\n"); |
| 381 | return 0; |
| 382 | } |
| 383 | |
| 384 | /* |
| 385 | * Get the interrupt status to know what happened (whether an error |
| 386 | * occurred and/or whether frames have been received successfully). |
| 387 | * When clearing the intr status register, clear only statuses that |
| 388 | * pertain to receive. |
| 389 | */ |
| 390 | intrstatus = in_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET); |
| 391 | /* |
| 392 | * Before reading from the length FIFO, make sure the length FIFO is not |
| 393 | * empty. We could cause an underrun error if we try to read from an |
| 394 | * empty FIFO. |
| 395 | */ |
| 396 | if (!(intrstatus & XEM_EIR_RECV_DONE_MASK)) { |
| 397 | /* debug ("Receiving FIFO is empty\n"); */ |
| 398 | return 0; |
| 399 | } |
| 400 | |
| 401 | /* |
| 402 | * Determine, from the MAC, the length of the next packet available |
| 403 | * in the data FIFO (there should be a non-zero length here) |
| 404 | */ |
| 405 | pktlength = in_be32 (emac.baseaddress + XEM_RPLR_OFFSET); |
| 406 | if (!pktlength) { |
| 407 | return 0; |
| 408 | } |
| 409 | |
| 410 | /* |
| 411 | * Write the RECV_DONE bit in the status register to clear it. This bit |
| 412 | * indicates the RPLR is non-empty, and we know it's set at this point. |
| 413 | * We clear it so that subsequent entry into this routine will reflect |
| 414 | * the current status. This is done because the non-empty bit is latched |
| 415 | * in the IPIF, which means it may indicate a non-empty condition even |
| 416 | * though there is something in the FIFO. |
| 417 | */ |
| 418 | out_be32 ((emac.baseaddress) + XIIF_V123B_IISR_OFFSET, |
| 419 | XEM_EIR_RECV_DONE_MASK); |
| 420 | |
| 421 | fifocount = in_be32 (emac.recvfifo.regbaseaddress + |
| 422 | XPF_COUNT_STATUS_REG_OFFSET) & XPF_COUNT_MASK; |
| 423 | |
| 424 | if ((fifocount * 4) < pktlength) { |
| 425 | debug ("Receiving FIFO is smaller than packet size.\n"); |
| 426 | return 0; |
| 427 | } |
| 428 | |
| 429 | wordcount = pktlength >> 2; |
| 430 | extrabytecount = pktlength & 0x3; |
| 431 | |
| 432 | for (fifocount = 0; fifocount < wordcount; fifocount++) { |
| 433 | etherrxbuff[fifocount] = |
| 434 | in_be32 (emac.recvfifo.databaseaddress); |
| 435 | } |
| 436 | |
| 437 | /* |
| 438 | * if there are extra bytes to handle, read the last word from the FIFO |
| 439 | * and insert the extra bytes into the buffer |
| 440 | */ |
| 441 | if (extrabytecount > 0) { |
| 442 | extrabytesbuffer = (u8 *) (etherrxbuff + wordcount); |
| 443 | |
| 444 | lastword = in_be32 (emac.recvfifo.databaseaddress); |
| 445 | |
| 446 | /* |
| 447 | * one extra byte in the last word, put the byte into the next |
| 448 | * location of the buffer, bytes in a word of the FIFO are |
| 449 | * ordered from most significant byte to least |
| 450 | */ |
| 451 | if (extrabytecount == 1) { |
| 452 | extrabytesbuffer[0] = (u8) (lastword >> 24); |
| 453 | } else if (extrabytecount == 2) { |
| 454 | extrabytesbuffer[0] = (u8) (lastword >> 24); |
| 455 | extrabytesbuffer[1] = (u8) (lastword >> 16); |
| 456 | } else if (extrabytecount == 3) { |
| 457 | extrabytesbuffer[0] = (u8) (lastword >> 24); |
| 458 | extrabytesbuffer[1] = (u8) (lastword >> 16); |
| 459 | extrabytesbuffer[2] = (u8) (lastword >> 8); |
| 460 | } |
| 461 | } |
| 462 | NetReceive((uchar *)etherrxbuff, pktlength); |
| 463 | return 1; |
| 464 | } |