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Matthias Fuchsc6c882e2007-12-28 17:07:14 +01001/*
Matthias Fuchs739a36f2009-09-30 11:55:04 +02002 * (C) Copyright 2009
3 * Matthias Fuchs, esd gmbh, matthias.fuchs@esd.eu
4 *
Matthias Fuchsc6c882e2007-12-28 17:07:14 +01005 * (C) Copyright 2006
6 * Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com
7 * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
8 * Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com
9 * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
10 * Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com
11 *
12 * (C) Copyright 2006-2007
13 * Stefan Roese, DENX Software Engineering, sr@denx.de.
14 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +020015 * SPDX-License-Identifier: GPL-2.0+
Matthias Fuchsc6c882e2007-12-28 17:07:14 +010016 */
17
18/* define DEBUG for debug output */
19#undef DEBUG
20
21#include <common.h>
22#include <asm/processor.h>
23#include <asm/io.h>
Matthias Fuchs739a36f2009-09-30 11:55:04 +020024#include <asm/mmu.h>
Stefan Roese247e9d72010-09-09 19:18:00 +020025#include <asm/ppc440.h>
Matthias Fuchsc6c882e2007-12-28 17:07:14 +010026
Simon Glass39f90ba2017-03-31 08:40:25 -060027DECLARE_GLOBAL_DATA_PTR;
28
Matthias Fuchs88f4a7b2008-01-02 16:48:34 +010029extern int denali_wait_for_dlllock(void);
30extern void denali_core_search_data_eye(void);
Matthias Fuchsc6c882e2007-12-28 17:07:14 +010031
Matthias Fuchs739a36f2009-09-30 11:55:04 +020032struct sdram_conf_s {
33 ulong size;
34 int rows;
35 int banks;
36};
Matthias Fuchsc6c882e2007-12-28 17:07:14 +010037
Matthias Fuchs739a36f2009-09-30 11:55:04 +020038struct sdram_conf_s sdram_conf[] = {
39 {(1024 << 20), 14, 8}, /* 1GByte: 4x2GBit, 14x10, 8 banks */
40 {(512 << 20), 13, 8}, /* 512MByte: 4x1GBit, 13x10, 8 banks */
41 {(256 << 20), 13, 4}, /* 256MByte: 4x512MBit, 13x10, 4 banks */
42};
Matthias Fuchsc6c882e2007-12-28 17:07:14 +010043
Matthias Fuchs739a36f2009-09-30 11:55:04 +020044/*
Matthias Fuchsc6c882e2007-12-28 17:07:14 +010045 * initdram -- 440EPx's DDR controller is a DENALI Core
Matthias Fuchs739a36f2009-09-30 11:55:04 +020046 */
47int initdram_by_rb(int rows, int banks)
Matthias Fuchsc6c882e2007-12-28 17:07:14 +010048{
Matthias Fuchsc6c882e2007-12-28 17:07:14 +010049 ulong speed = get_bus_freq(0);
Matthias Fuchsc6c882e2007-12-28 17:07:14 +010050
51 mtsdram(DDR0_02, 0x00000000);
52
53 mtsdram(DDR0_00, 0x0000190A);
54 mtsdram(DDR0_01, 0x01000000);
55 mtsdram(DDR0_03, 0x02030602);
56 mtsdram(DDR0_04, 0x0A020200);
57 mtsdram(DDR0_05, 0x02020308);
58 mtsdram(DDR0_06, 0x0102C812);
59 mtsdram(DDR0_07, 0x000D0100);
60 mtsdram(DDR0_08, 0x02430001);
61 mtsdram(DDR0_09, 0x00011D5F);
Stefan Roese1dcc5f12009-03-12 07:24:40 +010062 mtsdram(DDR0_10, 0x00000100);
Matthias Fuchsc6c882e2007-12-28 17:07:14 +010063 mtsdram(DDR0_11, 0x0027C800);
64 mtsdram(DDR0_12, 0x00000003);
65 mtsdram(DDR0_14, 0x00000000);
66 mtsdram(DDR0_17, 0x19000000);
67 mtsdram(DDR0_18, 0x19191919);
68 mtsdram(DDR0_19, 0x19191919);
69 mtsdram(DDR0_20, 0x0B0B0B0B);
70 mtsdram(DDR0_21, 0x0B0B0B0B);
71 mtsdram(DDR0_22, 0x00267F0B);
72 mtsdram(DDR0_23, 0x00000000);
73 mtsdram(DDR0_24, 0x01010002);
74 if (speed > 133333334)
75 mtsdram(DDR0_26, 0x5B26050C);
76 else
77 mtsdram(DDR0_26, 0x5B260408);
78 mtsdram(DDR0_27, 0x0000682B);
79 mtsdram(DDR0_28, 0x00000000);
80 mtsdram(DDR0_31, 0x00000000);
Matthias Fuchs739a36f2009-09-30 11:55:04 +020081
82 mtsdram(DDR0_42,
83 DDR0_42_ADDR_PINS_DECODE(14 - rows) |
84 0x00000006);
85 mtsdram(DDR0_43,
86 DDR0_43_EIGHT_BANK_MODE_ENCODE(8 == banks ? 1 : 0) |
87 0x030A0200);
88
Matthias Fuchsc6c882e2007-12-28 17:07:14 +010089 mtsdram(DDR0_44, 0x00000003);
90 mtsdram(DDR0_02, 0x00000001);
91
Matthias Fuchs88f4a7b2008-01-02 16:48:34 +010092 denali_wait_for_dlllock();
Matthias Fuchsc6c882e2007-12-28 17:07:14 +010093
94#ifdef CONFIG_DDR_DATA_EYE
Matthias Fuchs739a36f2009-09-30 11:55:04 +020095 /*
Matthias Fuchsc6c882e2007-12-28 17:07:14 +010096 * Perform data eye search if requested.
Matthias Fuchs739a36f2009-09-30 11:55:04 +020097 */
Matthias Fuchs88f4a7b2008-01-02 16:48:34 +010098 denali_core_search_data_eye();
Matthias Fuchsc6c882e2007-12-28 17:07:14 +010099#endif
Matthias Fuchs640b9e72008-01-11 14:55:08 +0100100 /*
101 * Clear possible errors resulting from data-eye-search.
102 * If not done, then we could get an interrupt later on when
103 * exceptions are enabled.
104 */
105 set_mcsr(get_mcsr());
106
Matthias Fuchs739a36f2009-09-30 11:55:04 +0200107 return 0;
108}
109
Simon Glass39f90ba2017-03-31 08:40:25 -0600110int initdram(void)
Matthias Fuchs739a36f2009-09-30 11:55:04 +0200111{
112 phys_size_t size;
113 int n;
114
115 /* go through supported memory configurations */
116 for (n = 0; n < ARRAY_SIZE(sdram_conf); n++) {
117 size = sdram_conf[n].size;
118
119 /* program TLB entries */
120 program_tlb(0, CONFIG_SYS_SDRAM_BASE, size,
121 TLB_WORD2_I_ENABLE);
122
123 /*
124 * setup denali core
125 */
126 initdram_by_rb(sdram_conf[n].rows,
127 sdram_conf[n].banks);
128
129 /* check for suitable configuration */
Simon Glass39f90ba2017-03-31 08:40:25 -0600130 if (get_ram_size(CONFIG_SYS_SDRAM_BASE, size) == size) {
131 gd->ram_size = size;
132 return 0;
133 }
Matthias Fuchs739a36f2009-09-30 11:55:04 +0200134
135 /* delete TLB entries */
136 remove_tlb(CONFIG_SYS_SDRAM_BASE, size);
137 }
138
Simon Glass39f90ba2017-03-31 08:40:25 -0600139 return -ENXIO;
Matthias Fuchsc6c882e2007-12-28 17:07:14 +0100140}