Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 393f9db5702e57e2cda5ecd4617c17817c7cf7fc / . / arch / arm / dts / r8a77995.dtsi
blob: d1a03cf8114021b0d0ad535de05f29967ecb52e0 [file] [log] [blame]
Marek Vasut04cd2e22017-10-08 20:52:52 +0200[diff] [blame]1/*
2 * Device Tree Source for the r8a77995 SoC
3 *
4 * Copyright (C) 2016 Renesas Electronics Corp.
5 * Copyright (C) 2017 Glider bvba
6 *
Marek Vasut07efb452017-11-29 04:27:36 +0100[diff] [blame]7 * SPDX-License-Identifier: GPL-2.0
Marek Vasut04cd2e22017-10-08 20:52:52 +0200[diff] [blame]8 */
9
10#include <dt-bindings/clock/r8a77995-cpg-mssr.h>
11#include <dt-bindings/interrupt-controller/arm-gic.h>
12#include <dt-bindings/power/r8a77995-sysc.h>
13
14/ {
15 compatible = "renesas,r8a77995";
16 #address-cells = <2>;
17 #size-cells = <2>;
18
19 psci {
20 compatible = "arm,psci-1.0", "arm,psci-0.2";
21 method = "smc";
22 };
23
24 cpus {
25 #address-cells = <1>;
26 #size-cells = <0>;
27
28 a53_0: cpu@0 {
29 compatible = "arm,cortex-a53", "arm,armv8";
30 reg = <0x0>;
31 device_type = "cpu";
32 power-domains = <&sysc R8A77995_PD_CA53_CPU0>;
33 next-level-cache = <&L2_CA53>;
34 enable-method = "psci";
35 };
36
37 L2_CA53: cache-controller-1 {
38 compatible = "cache";
39 power-domains = <&sysc R8A77995_PD_CA53_SCU>;
40 cache-unified;
41 cache-level = <2>;
42 };
43 };
44
45 extal_clk: extal {
46 compatible = "fixed-clock";
47 #clock-cells = <0>;
48 /* This value must be overridden by the board */
49 clock-frequency = <0>;
Marek Vasut04cd2e22017-10-08 20:52:52 +0200[diff] [blame]50 };
51
52 scif_clk: scif {
53 compatible = "fixed-clock";
54 #clock-cells = <0>;
55 clock-frequency = <0>;
56 };
57
58 soc {
59 compatible = "simple-bus";
60 interrupt-parent = <&gic>;
61 #address-cells = <2>;
62 #size-cells = <2>;
63 ranges;
Marek Vasut04cd2e22017-10-08 20:52:52 +0200[diff] [blame]64
65 gic: interrupt-controller@f1010000 {
66 compatible = "arm,gic-400";
67 #interrupt-cells = <3>;
68 #address-cells = <0>;
69 interrupt-controller;
70 reg = <0x0 0xf1010000 0 0x1000>,
71 <0x0 0xf1020000 0 0x20000>,
72 <0x0 0xf1040000 0 0x20000>,
73 <0x0 0xf1060000 0 0x20000>;
74 interrupts = <GIC_PPI 9
75 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
76 clocks = <&cpg CPG_MOD 408>;
77 clock-names = "clk";
78 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
79 resets = <&cpg 408>;
80 };
81
82 timer {
83 compatible = "arm,armv8-timer";
84 interrupts = <GIC_PPI 13
85 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
86 <GIC_PPI 14
87 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
88 <GIC_PPI 11
89 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
90 <GIC_PPI 10
91 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
92 };
93
94 rwdt: watchdog@e6020000 {
95 compatible = "renesas,r8a77995-wdt",
96 "renesas,rcar-gen3-wdt";
97 reg = <0 0xe6020000 0 0x0c>;
98 clocks = <&cpg CPG_MOD 402>;
99 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
100 resets = <&cpg 402>;
101 status = "disabled";
102 };
103
104 pmu_a53 {
105 compatible = "arm,cortex-a53-pmu";
106 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
107 };
108
109 cpg: clock-controller@e6150000 {
110 compatible = "renesas,r8a77995-cpg-mssr";
111 reg = <0 0xe6150000 0 0x1000>;
112 clocks = <&extal_clk>;
113 clock-names = "extal";
114 #clock-cells = <2>;
115 #power-domain-cells = <0>;
116 #reset-cells = <1>;
Marek Vasut04cd2e22017-10-08 20:52:52 +0200[diff] [blame]117 };
118
119 rst: reset-controller@e6160000 {
120 compatible = "renesas,r8a77995-rst";
121 reg = <0 0xe6160000 0 0x0200>;
122 };
123
124 pfc: pin-controller@e6060000 {
125 compatible = "renesas,pfc-r8a77995";
126 reg = <0 0xe6060000 0 0x508>;
127 };
128
129 prr: chipid@fff00044 {
130 compatible = "renesas,prr";
131 reg = <0 0xfff00044 0 4>;
Marek Vasut04cd2e22017-10-08 20:52:52 +0200[diff] [blame]132 };
133
134 sysc: system-controller@e6180000 {
135 compatible = "renesas,r8a77995-sysc";
136 reg = <0 0xe6180000 0 0x0400>;
137 #power-domain-cells = <1>;
138 };
139
140 intc_ex: interrupt-controller@e61c0000 {
141 compatible = "renesas,intc-ex-r8a77995", "renesas,irqc";
142 #interrupt-cells = <2>;
143 interrupt-controller;
144 reg = <0 0xe61c0000 0 0x200>;
145 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
146 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
147 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
148 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
149 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
150 GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
151 clocks = <&cpg CPG_MOD 407>;
152 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
153 resets = <&cpg 407>;
154 };
155
156 gpio0: gpio@e6050000 {
157 compatible = "renesas,gpio-r8a77995",
158 "renesas,rcar-gen3-gpio",
159 "renesas,gpio-rcar";
160 reg = <0 0xe6050000 0 0x50>;
161 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
162 #gpio-cells = <2>;
163 gpio-controller;
164 gpio-ranges = <&pfc 0 0 9>;
165 #interrupt-cells = <2>;
166 interrupt-controller;
167 clocks = <&cpg CPG_MOD 912>;
168 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
169 resets = <&cpg 912>;
170 };
171
172 gpio1: gpio@e6051000 {
173 compatible = "renesas,gpio-r8a77995",
174 "renesas,rcar-gen3-gpio",
175 "renesas,gpio-rcar";
176 reg = <0 0xe6051000 0 0x50>;
177 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
178 #gpio-cells = <2>;
179 gpio-controller;
180 gpio-ranges = <&pfc 0 32 32>;
181 #interrupt-cells = <2>;
182 interrupt-controller;
183 clocks = <&cpg CPG_MOD 911>;
184 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
185 resets = <&cpg 911>;
186 };
187
188 gpio2: gpio@e6052000 {
189 compatible = "renesas,gpio-r8a77995",
190 "renesas,rcar-gen3-gpio",
191 "renesas,gpio-rcar";
192 reg = <0 0xe6052000 0 0x50>;
193 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
194 #gpio-cells = <2>;
195 gpio-controller;
196 gpio-ranges = <&pfc 0 64 32>;
197 #interrupt-cells = <2>;
198 interrupt-controller;
199 clocks = <&cpg CPG_MOD 910>;
200 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
201 resets = <&cpg 910>;
202 };
203
204 gpio3: gpio@e6053000 {
205 compatible = "renesas,gpio-r8a77995",
206 "renesas,rcar-gen3-gpio",
207 "renesas,gpio-rcar";
208 reg = <0 0xe6053000 0 0x50>;
209 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
210 #gpio-cells = <2>;
211 gpio-controller;
212 gpio-ranges = <&pfc 0 96 10>;
213 #interrupt-cells = <2>;
214 interrupt-controller;
215 clocks = <&cpg CPG_MOD 909>;
216 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
217 resets = <&cpg 909>;
218 };
219
220 gpio4: gpio@e6054000 {
221 compatible = "renesas,gpio-r8a77995",
222 "renesas,rcar-gen3-gpio",
223 "renesas,gpio-rcar";
224 reg = <0 0xe6054000 0 0x50>;
225 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
226 #gpio-cells = <2>;
227 gpio-controller;
228 gpio-ranges = <&pfc 0 128 32>;
229 #interrupt-cells = <2>;
230 interrupt-controller;
231 clocks = <&cpg CPG_MOD 908>;
232 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
233 resets = <&cpg 908>;
234 };
235
236 gpio5: gpio@e6055000 {
237 compatible = "renesas,gpio-r8a77995",
238 "renesas,rcar-gen3-gpio",
239 "renesas,gpio-rcar";
240 reg = <0 0xe6055000 0 0x50>;
241 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
242 #gpio-cells = <2>;
243 gpio-controller;
244 gpio-ranges = <&pfc 0 160 21>;
245 #interrupt-cells = <2>;
246 interrupt-controller;
247 clocks = <&cpg CPG_MOD 907>;
248 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
249 resets = <&cpg 907>;
250 };
251
252 gpio6: gpio@e6055400 {
253 compatible = "renesas,gpio-r8a77995",
254 "renesas,rcar-gen3-gpio",
255 "renesas,gpio-rcar";
256 reg = <0 0xe6055400 0 0x50>;
257 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
258 #gpio-cells = <2>;
259 gpio-controller;
260 gpio-ranges = <&pfc 0 192 14>;
261 #interrupt-cells = <2>;
262 interrupt-controller;
263 clocks = <&cpg CPG_MOD 906>;
264 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
265 resets = <&cpg 906>;
266 };
267
268 avb: ethernet@e6800000 {
269 compatible = "renesas,etheravb-r8a77995",
270 "renesas,etheravb-rcar-gen3";
271 reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
272 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
273 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
274 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
275 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
276 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
277 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
278 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
279 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
280 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
281 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
282 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
283 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
284 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
285 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
286 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
287 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
288 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
289 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
290 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
291 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
292 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
293 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
294 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
295 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
296 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
297 interrupt-names = "ch0", "ch1", "ch2", "ch3",
298 "ch4", "ch5", "ch6", "ch7",
299 "ch8", "ch9", "ch10", "ch11",
300 "ch12", "ch13", "ch14", "ch15",
301 "ch16", "ch17", "ch18", "ch19",
302 "ch20", "ch21", "ch22", "ch23",
303 "ch24";
304 clocks = <&cpg CPG_MOD 812>;
305 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
306 resets = <&cpg 812>;
307 phy-mode = "rgmii-txid";
308 #address-cells = <1>;
309 #size-cells = <0>;
310 status = "disabled";
311 };
312
313 scif2: serial@e6e88000 {
314 compatible = "renesas,scif-r8a77995",
315 "renesas,rcar-gen3-scif", "renesas,scif";
316 reg = <0 0xe6e88000 0 64>;
317 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
318 clocks = <&cpg CPG_MOD 310>,
319 <&cpg CPG_CORE R8A77995_CLK_S3D1C>,
320 <&scif_clk>;
321 clock-names = "fck", "brg_int", "scif_clk";
322 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
323 resets = <&cpg 310>;
324 status = "disabled";
325 };
326
327 pwm0: pwm@e6e30000 {
328 compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
329 reg = <0 0xe6e30000 0 0x8>;
330 #pwm-cells = <2>;
331 clocks = <&cpg CPG_MOD 523>;
332 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
333 resets = <&cpg 523>;
334 status = "disabled";
335 };
336
337 pwm1: pwm@e6e31000 {
338 compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
339 reg = <0 0xe6e31000 0 0x8>;
340 #pwm-cells = <2>;
341 clocks = <&cpg CPG_MOD 523>;
342 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
343 resets = <&cpg 523>;
344 status = "disabled";
345 };
346
347 pwm2: pwm@e6e32000 {
348 compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
349 reg = <0 0xe6e32000 0 0x8>;
350 #pwm-cells = <2>;
351 clocks = <&cpg CPG_MOD 523>;
352 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
353 resets = <&cpg 523>;
354 status = "disabled";
355 };
356
357 pwm3: pwm@e6e33000 {
358 compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
359 reg = <0 0xe6e33000 0 0x8>;
360 #pwm-cells = <2>;
361 clocks = <&cpg CPG_MOD 523>;
362 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
363 resets = <&cpg 523>;
364 status = "disabled";
365 };
366
367 ehci0: usb@ee080100 {
368 compatible = "generic-ehci";
369 reg = <0 0xee080100 0 0x100>;
370 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
371 clocks = <&cpg CPG_MOD 703>;
372 phys = <&usb2_phy0>;
373 phy-names = "usb";
374 companion = <&ohci0>;
375 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
376 resets = <&cpg 703>;
377 status = "disabled";
378 };
379
380 ohci0: usb@ee080000 {
381 compatible = "generic-ohci";
382 reg = <0 0xee080000 0 0x100>;
383 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
384 clocks = <&cpg CPG_MOD 703>;
385 phys = <&usb2_phy0>;
386 phy-names = "usb";
387 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
388 resets = <&cpg 703>;
389 status = "disabled";
390 };
391
392 usb2_phy0: usb-phy@ee080200 {
393 compatible = "renesas,usb2-phy-r8a77995",
394 "renesas,rcar-gen3-usb2-phy";
395 reg = <0 0xee080200 0 0x700>;
396 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
397 clocks = <&cpg CPG_MOD 703>;
398 power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
399 resets = <&cpg 703>;
400 #phy-cells = <0>;
401 status = "disabled";
402 };
403 };
404};