| Luca Ceresoli | 202a76b | 2011-04-19 09:48:51 -0400 | [diff] [blame] | 1 | /* |
| 2 | * (c) 2011 Comelit Group SpA, Luca Ceresoli <luca.ceresoli@comelit.it> |
| 3 | * |
| Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 4 | * SPDX-License-Identifier: GPL-2.0+ |
| Luca Ceresoli | 202a76b | 2011-04-19 09:48:51 -0400 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #ifndef _OMAP3_REGS_H |
| 8 | #define _OMAP3_REGS_H |
| 9 | |
| 10 | /* |
| 11 | * Register definitions for OMAP3 processors. |
| 12 | */ |
| 13 | |
| 14 | /* |
| 15 | * GPMC_CONFIG1 - GPMC_CONFIG7 |
| 16 | */ |
| 17 | |
| 18 | /* Values for GPMC_CONFIG1 - signal control parameters */ |
| 19 | #define WRAPBURST (1 << 31) |
| 20 | #define READMULTIPLE (1 << 30) |
| 21 | #define READTYPE (1 << 29) |
| 22 | #define WRITEMULTIPLE (1 << 28) |
| 23 | #define WRITETYPE (1 << 27) |
| 24 | #define CLKACTIVATIONTIME(x) (((x) & 3) << 25) |
| 25 | #define ATTACHEDDEVICEPAGELENGTH(x) (((x) & 3) << 23) |
| 26 | #define WAITREADMONITORING (1 << 22) |
| 27 | #define WAITWRITEMONITORING (1 << 21) |
| 28 | #define WAITMONITORINGTIME(x) (((x) & 3) << 18) |
| 29 | #define WAITPINSELECT(x) (((x) & 3) << 16) |
| 30 | #define DEVICESIZE(x) (((x) & 3) << 12) |
| 31 | #define DEVICESIZE_8BIT DEVICESIZE(0) |
| 32 | #define DEVICESIZE_16BIT DEVICESIZE(1) |
| 33 | #define DEVICETYPE(x) (((x) & 3) << 10) |
| 34 | #define DEVICETYPE_NOR DEVICETYPE(0) |
| 35 | #define DEVICETYPE_NAND DEVICETYPE(2) |
| 36 | #define MUXADDDATA (1 << 9) |
| 37 | #define TIMEPARAGRANULARITY (1 << 4) |
| 38 | #define GPMCFCLKDIVIDER(x) (((x) & 3) << 0) |
| 39 | |
| 40 | /* Values for GPMC_CONFIG2 - CS timing */ |
| 41 | #define CSWROFFTIME(x) (((x) & 0x1f) << 16) |
| 42 | #define CSRDOFFTIME(x) (((x) & 0x1f) << 8) |
| 43 | #define CSEXTRADELAY (1 << 7) |
| 44 | #define CSONTIME(x) (((x) & 0xf) << 0) |
| 45 | |
| 46 | /* Values for GPMC_CONFIG3 - nADV timing */ |
| 47 | #define ADVWROFFTIME(x) (((x) & 0x1f) << 16) |
| 48 | #define ADVRDOFFTIME(x) (((x) & 0x1f) << 8) |
| 49 | #define ADVEXTRADELAY (1 << 7) |
| 50 | #define ADVONTIME(x) (((x) & 0xf) << 0) |
| 51 | |
| 52 | /* Values for GPMC_CONFIG4 - nWE and nOE timing */ |
| 53 | #define WEOFFTIME(x) (((x) & 0x1f) << 24) |
| 54 | #define WEEXTRADELAY (1 << 23) |
| 55 | #define WEONTIME(x) (((x) & 0xf) << 16) |
| 56 | #define OEOFFTIME(x) (((x) & 0x1f) << 8) |
| 57 | #define OEEXTRADELAY (1 << 7) |
| 58 | #define OEONTIME(x) (((x) & 0xf) << 0) |
| 59 | |
| 60 | /* Values for GPMC_CONFIG5 - RdAccessTime and CycleTime timing */ |
| 61 | #define PAGEBURSTACCESSTIME(x) (((x) & 0xf) << 24) |
| 62 | #define RDACCESSTIME(x) (((x) & 0x1f) << 16) |
| 63 | #define WRCYCLETIME(x) (((x) & 0x1f) << 8) |
| 64 | #define RDCYCLETIME(x) (((x) & 0x1f) << 0) |
| 65 | |
| 66 | /* Values for GPMC_CONFIG6 - misc timings */ |
| 67 | #define WRACCESSTIME(x) (((x) & 0x1f) << 24) |
| 68 | #define WRDATAONADMUXBUS(x) (((x) & 0xf) << 16) |
| 69 | #define CYCLE2CYCLEDELAY(x) (((x) & 0xf) << 8) |
| 70 | #define CYCLE2CYCLESAMECSEN (1 << 7) |
| 71 | #define CYCLE2CYCLEDIFFCSEN (1 << 6) |
| 72 | #define BUSTURNAROUND(x) (((x) & 0xf) << 0) |
| 73 | |
| 74 | /* Values for GPMC_CONFIG7 - CS address mapping configuration */ |
| 75 | #define MASKADDRESS(x) (((x) & 0xf) << 8) |
| 76 | #define CSVALID (1 << 6) |
| 77 | #define BASEADDRESS(x) (((x) & 0x3f) << 0) |
| 78 | |
| 79 | #endif /* _OMAP3_REGS_H */ |