| Sricharan | 9310ff7 | 2011-11-15 09:49:55 -0500 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2010 |
| 3 | * Texas Instruments Incorporated, <www.ti.com> |
| 4 | * |
| 5 | * Balaji Krishnamoorthy <balajitk@ti.com> |
| 6 | * Aneesh V <aneesh@ti.com> |
| 7 | * |
| 8 | * See file CREDITS for list of people who contributed to this |
| 9 | * project. |
| 10 | * |
| 11 | * This program is free software; you can redistribute it and/or |
| 12 | * modify it under the terms of the GNU General Public License as |
| 13 | * published by the Free Software Foundation; either version 2 of |
| 14 | * the License, or (at your option) any later version. |
| 15 | * |
| 16 | * This program is distributed in the hope that it will be useful, |
| 17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 19 | * GNU General Public License for more details. |
| 20 | * |
| 21 | * You should have received a copy of the GNU General Public License |
| 22 | * along with this program; if not, write to the Free Software |
| 23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 24 | * MA 02111-1307 USA |
| 25 | */ |
| 26 | #ifndef _EVM5430_MUX_DATA_H |
| 27 | #define _EVM5430_MUX_DATA_H |
| 28 | |
| 29 | #include <asm/arch/mux_omap5.h> |
| 30 | |
| 31 | const struct pad_conf_entry core_padconf_array_essential[] = { |
| 32 | |
| 33 | {GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat0 */ |
| 34 | {GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat1 */ |
| 35 | {GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat2 */ |
| 36 | {GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat3 */ |
| 37 | {GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat4 */ |
| 38 | {GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat5 */ |
| 39 | {GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat6 */ |
| 40 | {GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat7 */ |
| 41 | {GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)}, /* sdmmc2_clk */ |
| 42 | {GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_cmd */ |
| 43 | {SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc1_clk */ |
| 44 | {SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_cmd */ |
| 45 | {SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat0 */ |
| 46 | {SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat1 */ |
| 47 | {SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat2 */ |
| 48 | {SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat3 */ |
| 49 | {SDMMC1_DAT4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat4 */ |
| 50 | {SDMMC1_DAT5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat5 */ |
| 51 | {SDMMC1_DAT6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat6 */ |
| 52 | {SDMMC1_DAT7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat7 */ |
| Sricharan | 9310ff7 | 2011-11-15 09:49:55 -0500 | [diff] [blame] | 53 | {UART3_CTS_RCTX, (PTU | IEN | M0)}, /* uart3_tx */ |
| 54 | {UART3_RTS_SD, (M0)}, /* uart3_rts_sd */ |
| 55 | {UART3_RX_IRRX, (IEN | M0)}, /* uart3_rx */ |
| 56 | {UART3_TX_IRTX, (M0)} /* uart3_tx */ |
| 57 | |
| 58 | }; |
| 59 | |
| 60 | const struct pad_conf_entry wkup_padconf_array_essential[] = { |
| 61 | |
| 62 | {PAD1_SR_SCL, (PTU | IEN | M0)}, /* sr_scl */ |
| 63 | {PAD0_SR_SDA, (PTU | IEN | M0)}, /* sr_sda */ |
| 64 | {PAD1_SYS_32K, (IEN | M0)} /* sys_32k */ |
| 65 | |
| 66 | }; |
| 67 | |
| 68 | const struct pad_conf_entry core_padconf_array_non_essential[] = { |
| 69 | {GPMC_AD8, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* gpio_32 */ |
| 70 | {GPMC_AD9, (PTU | IEN | M3)}, /* gpio_33 */ |
| 71 | {GPMC_AD10, (PTU | IEN | M3)}, /* gpio_34 */ |
| 72 | {GPMC_AD11, (PTU | IEN | M3)}, /* gpio_35 */ |
| 73 | {GPMC_AD12, (PTU | IEN | M3)}, /* gpio_36 */ |
| 74 | {GPMC_AD13, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_37 */ |
| 75 | {GPMC_AD14, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_38 */ |
| 76 | {GPMC_AD15, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_39 */ |
| 77 | {GPMC_A16, (M3)}, /* gpio_40 */ |
| 78 | {GPMC_A17, (PTD | M3)}, /* gpio_41 */ |
| 79 | {GPMC_A18, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row6 */ |
| 80 | {GPMC_A19, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row7 */ |
| 81 | {GPMC_A20, (IEN | M3)}, /* gpio_44 */ |
| 82 | {GPMC_A21, (M3)}, /* gpio_45 */ |
| 83 | {GPMC_A22, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col6 */ |
| 84 | {GPMC_A23, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col7 */ |
| 85 | {GPMC_A24, (PTD | M3)}, /* gpio_48 */ |
| 86 | {GPMC_A25, (PTD | M3)}, /* gpio_49 */ |
| 87 | {GPMC_NCS0, (M3)}, /* gpio_50 */ |
| 88 | {GPMC_NCS1, (IEN | M3)}, /* gpio_51 */ |
| 89 | {GPMC_NCS2, (IEN | M3)}, /* gpio_52 */ |
| 90 | {GPMC_NCS3, (IEN | M3)}, /* gpio_53 */ |
| 91 | {GPMC_NWP, (M3)}, /* gpio_54 */ |
| 92 | {GPMC_CLK, (PTD | M3)}, /* gpio_55 */ |
| 93 | {GPMC_NADV_ALE, (M3)}, /* gpio_56 */ |
| 94 | {GPMC_NBE0_CLE, (M3)}, /* gpio_59 */ |
| 95 | {GPMC_NBE1, (PTD | M3)}, /* gpio_60 */ |
| 96 | {GPMC_WAIT0, (PTU | IEN | M3)}, /* gpio_61 */ |
| 97 | {GPMC_WAIT1, (IEN | M3)}, /* gpio_62 */ |
| 98 | {C2C_DATA11, (PTD | M3)}, /* gpio_100 */ |
| 99 | {C2C_DATA12, (M1)}, /* dsi1_te0 */ |
| 100 | {C2C_DATA13, (PTD | M3)}, /* gpio_102 */ |
| 101 | {C2C_DATA14, (M1)}, /* dsi2_te0 */ |
| 102 | {C2C_DATA15, (PTD | M3)}, /* gpio_104 */ |
| 103 | {HDMI_HPD, (M0)}, /* hdmi_hpd */ |
| 104 | {HDMI_CEC, (M0)}, /* hdmi_cec */ |
| 105 | {HDMI_DDC_SCL, (PTU | M0)}, /* hdmi_ddc_scl */ |
| 106 | {HDMI_DDC_SDA, (PTU | IEN | M0)}, /* hdmi_ddc_sda */ |
| 107 | {CSI21_DX0, (IEN | M0)}, /* csi21_dx0 */ |
| 108 | {CSI21_DY0, (IEN | M0)}, /* csi21_dy0 */ |
| 109 | {CSI21_DX1, (IEN | M0)}, /* csi21_dx1 */ |
| 110 | {CSI21_DY1, (IEN | M0)}, /* csi21_dy1 */ |
| 111 | {CSI21_DX2, (IEN | M0)}, /* csi21_dx2 */ |
| 112 | {CSI21_DY2, (IEN | M0)}, /* csi21_dy2 */ |
| 113 | {CSI21_DX3, (PTD | M7)}, /* csi21_dx3 */ |
| 114 | {CSI21_DY3, (PTD | M7)}, /* csi21_dy3 */ |
| 115 | {CSI21_DX4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)}, /* csi21_dx4 */ |
| 116 | {CSI21_DY4, (PTD | OFF_EN | OFF_PD | OFF_IN | M7)}, /* csi21_dy4 */ |
| 117 | {CSI22_DX0, (IEN | M0)}, /* csi22_dx0 */ |
| 118 | {CSI22_DY0, (IEN | M0)}, /* csi22_dy0 */ |
| 119 | {CSI22_DX1, (IEN | M0)}, /* csi22_dx1 */ |
| 120 | {CSI22_DY1, (IEN | M0)}, /* csi22_dy1 */ |
| 121 | {CAM_SHUTTER, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* cam_shutter */ |
| 122 | {CAM_STROBE, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* cam_strobe */ |
| 123 | {CAM_GLOBALRESET, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)}, /* gpio_83 */ |
| 124 | {USBB1_ULPITLL_CLK, (IEN | OFF_EN | OFF_IN | M1)}, /* hsi1_cawake */ |
| 125 | {USBB1_ULPITLL_STP, (IEN | OFF_EN | OFF_IN | M1)}, /* hsi1_cadata */ |
| 126 | {USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_IN | M1)}, /* hsi1_caflag */ |
| 127 | {USBB1_ULPITLL_NXT, (OFF_EN | M1)}, /* hsi1_acready */ |
| 128 | {USBB1_ULPITLL_DAT0, (OFF_EN | M1)}, /* hsi1_acwake */ |
| 129 | {USBB1_ULPITLL_DAT1, (OFF_EN | M1)}, /* hsi1_acdata */ |
| 130 | {USBB1_ULPITLL_DAT2, (OFF_EN | M1)}, /* hsi1_acflag */ |
| 131 | {USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_IN | M1)}, /* hsi1_caready */ |
| 132 | {USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat4 */ |
| 133 | {USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat5 */ |
| 134 | {USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat6 */ |
| 135 | {USBB1_ULPITLL_DAT7, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)}, /* usbb1_ulpiphy_dat7 */ |
| 136 | {USBB1_HSIC_DATA, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usbb1_hsic_data */ |
| 137 | {USBB1_HSIC_STROBE, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usbb1_hsic_strobe */ |
| 138 | {USBC1_ICUSB_DP, (IEN | M0)}, /* usbc1_icusb_dp */ |
| 139 | {USBC1_ICUSB_DM, (IEN | M0)}, /* usbc1_icusb_dm */ |
| 140 | {ABE_MCBSP2_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_clkx */ |
| 141 | {ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dr */ |
| 142 | {ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp2_dx */ |
| 143 | {ABE_MCBSP2_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp2_fsx */ |
| 144 | {ABE_MCBSP1_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp1_clkx */ |
| 145 | {ABE_MCBSP1_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp1_dr */ |
| 146 | {ABE_MCBSP1_DX, (OFF_EN | OFF_OUT_PTD | M0)}, /* abe_mcbsp1_dx */ |
| 147 | {ABE_MCBSP1_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_mcbsp1_fsx */ |
| 148 | {ABE_PDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_ul_data */ |
| 149 | {ABE_PDM_DL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_dl_data */ |
| 150 | {ABE_PDM_FRAME, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_frame */ |
| 151 | {ABE_PDM_LB_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_pdm_lb_clk */ |
| 152 | {ABE_CLKS, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* abe_clks */ |
| 153 | {ABE_DMIC_CLK1, (M0)}, /* abe_dmic_clk1 */ |
| 154 | {ABE_DMIC_DIN1, (IEN | M0)}, /* abe_dmic_din1 */ |
| 155 | {ABE_DMIC_DIN2, (IEN | M0)}, /* abe_dmic_din2 */ |
| 156 | {ABE_DMIC_DIN3, (IEN | M0)}, /* abe_dmic_din3 */ |
| 157 | {UART2_CTS, (PTU | IEN | M0)}, /* uart2_cts */ |
| 158 | {UART2_RTS, (M0)}, /* uart2_rts */ |
| 159 | {UART2_RX, (PTU | IEN | M0)}, /* uart2_rx */ |
| 160 | {UART2_TX, (M0)}, /* uart2_tx */ |
| 161 | {HDQ_SIO, (M3)}, /* gpio_127 */ |
| 162 | {MCSPI1_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_clk */ |
| 163 | {MCSPI1_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_somi */ |
| 164 | {MCSPI1_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_simo */ |
| 165 | {MCSPI1_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_cs0 */ |
| 166 | {MCSPI1_CS1, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3)}, /* mcspi1_cs1 */ |
| 167 | {MCSPI1_CS2, (PTU | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_139 */ |
| 168 | {MCSPI1_CS3, (PTU | IEN | M3)}, /* gpio_140 */ |
| 169 | {SDMMC5_CLK, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc5_clk */ |
| 170 | {SDMMC5_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_cmd */ |
| 171 | {SDMMC5_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat0 */ |
| 172 | {SDMMC5_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat1 */ |
| 173 | {SDMMC5_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat2 */ |
| 174 | {SDMMC5_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc5_dat3 */ |
| 175 | {MCSPI4_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_clk */ |
| 176 | {MCSPI4_SIMO, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_simo */ |
| 177 | {MCSPI4_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_somi */ |
| 178 | {MCSPI4_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi4_cs0 */ |
| 179 | {UART4_RX, (IEN | M0)}, /* uart4_rx */ |
| 180 | {UART4_TX, (M0)}, /* uart4_tx */ |
| 181 | {USBB2_ULPITLL_CLK, (PTD | IEN | M3)}, /* gpio_157 */ |
| 182 | {USBB2_ULPITLL_STP, (IEN | M5)}, /* dispc2_data23 */ |
| 183 | {USBB2_ULPITLL_DIR, (IEN | M5)}, /* dispc2_data22 */ |
| 184 | {USBB2_ULPITLL_NXT, (IEN | M5)}, /* dispc2_data21 */ |
| 185 | {USBB2_ULPITLL_DAT0, (IEN | M5)}, /* dispc2_data20 */ |
| 186 | {USBB2_ULPITLL_DAT1, (IEN | M5)}, /* dispc2_data19 */ |
| 187 | {USBB2_ULPITLL_DAT2, (IEN | M5)}, /* dispc2_data18 */ |
| 188 | {USBB2_ULPITLL_DAT3, (IEN | M5)}, /* dispc2_data15 */ |
| 189 | {USBB2_ULPITLL_DAT4, (IEN | M5)}, /* dispc2_data14 */ |
| 190 | {USBB2_ULPITLL_DAT5, (IEN | M5)}, /* dispc2_data13 */ |
| 191 | {USBB2_ULPITLL_DAT6, (IEN | M5)}, /* dispc2_data12 */ |
| 192 | {USBB2_ULPITLL_DAT7, (IEN | M5)}, /* dispc2_data11 */ |
| 193 | {USBB2_HSIC_DATA, (PTD | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_169 */ |
| 194 | {USBB2_HSIC_STROBE, (PTD | OFF_EN | OFF_OUT_PTU | M3)}, /* gpio_170 */ |
| 195 | {UNIPRO_TX0, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col0 */ |
| 196 | {UNIPRO_TY0, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col1 */ |
| 197 | {UNIPRO_TX1, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col2 */ |
| 198 | {UNIPRO_TY1, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col3 */ |
| 199 | {UNIPRO_TX2, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col4 */ |
| 200 | {UNIPRO_TY2, (OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_col5 */ |
| 201 | {UNIPRO_RX0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row0 */ |
| 202 | {UNIPRO_RY0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row1 */ |
| 203 | {UNIPRO_RX1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row2 */ |
| 204 | {UNIPRO_RY1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row3 */ |
| 205 | {UNIPRO_RX2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row4 */ |
| 206 | {UNIPRO_RY2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* kpd_row5 */ |
| 207 | {USBA0_OTG_CE, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0)}, /* usba0_otg_ce */ |
| 208 | {USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dp */ |
| 209 | {USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* usba0_otg_dm */ |
| 210 | {FREF_CLK1_OUT, (M0)}, /* fref_clk1_out */ |
| 211 | {FREF_CLK2_OUT, (M0)}, /* fref_clk2_out */ |
| 212 | {SYS_NIRQ1, (PTU | IEN | M0)}, /* sys_nirq1 */ |
| 213 | {SYS_NIRQ2, (M7)}, /* sys_nirq2 */ |
| 214 | {SYS_BOOT0, (PTU | IEN | M3)}, /* gpio_184 */ |
| 215 | {SYS_BOOT1, (M3)}, /* gpio_185 */ |
| 216 | {SYS_BOOT2, (PTD | IEN | M3)}, /* gpio_186 */ |
| 217 | {SYS_BOOT3, (PTD | IEN | M3)}, /* gpio_187 */ |
| 218 | {SYS_BOOT4, (M3)}, /* gpio_188 */ |
| 219 | {SYS_BOOT5, (PTD | IEN | M3)}, /* gpio_189 */ |
| 220 | {DPM_EMU0, (IEN | M0)}, /* dpm_emu0 */ |
| 221 | {DPM_EMU1, (IEN | M0)}, /* dpm_emu1 */ |
| 222 | {DPM_EMU2, (IEN | M0)}, /* dpm_emu2 */ |
| 223 | {DPM_EMU3, (IEN | M5)}, /* dispc2_data10 */ |
| 224 | {DPM_EMU4, (IEN | M5)}, /* dispc2_data9 */ |
| 225 | {DPM_EMU5, (IEN | M5)}, /* dispc2_data16 */ |
| 226 | {DPM_EMU6, (IEN | M5)}, /* dispc2_data17 */ |
| 227 | {DPM_EMU7, (IEN | M5)}, /* dispc2_hsync */ |
| 228 | {DPM_EMU8, (IEN | M5)}, /* dispc2_pclk */ |
| 229 | {DPM_EMU9, (IEN | M5)}, /* dispc2_vsync */ |
| 230 | {DPM_EMU10, (IEN | M5)}, /* dispc2_de */ |
| 231 | {DPM_EMU11, (IEN | M5)}, /* dispc2_data8 */ |
| 232 | {DPM_EMU12, (IEN | M5)}, /* dispc2_data7 */ |
| 233 | {DPM_EMU13, (IEN | M5)}, /* dispc2_data6 */ |
| 234 | {DPM_EMU14, (IEN | M5)}, /* dispc2_data5 */ |
| 235 | {DPM_EMU15, (IEN | M5)}, /* dispc2_data4 */ |
| 236 | {DPM_EMU16, (M3)}, /* gpio_27 */ |
| 237 | {DPM_EMU17, (IEN | M5)}, /* dispc2_data2 */ |
| 238 | {DPM_EMU18, (IEN | M5)}, /* dispc2_data1 */ |
| 239 | {DPM_EMU19, (IEN | M5)}, /* dispc2_data0 */ |
| Sricharan | 308fe92 | 2011-11-15 09:50:03 -0500 | [diff] [blame] | 240 | {I2C1_SCL, (PTU | IEN | M0)}, /* i2c1_scl */ |
| 241 | {I2C1_SDA, (PTU | IEN | M0)}, /* i2c1_sda */ |
| 242 | {I2C2_SCL, (PTU | IEN | M0)}, /* i2c2_scl */ |
| 243 | {I2C2_SDA, (PTU | IEN | M0)}, /* i2c2_sda */ |
| 244 | {I2C3_SCL, (PTU | IEN | M0)}, /* i2c3_scl */ |
| 245 | {I2C3_SDA, (PTU | IEN | M0)}, /* i2c3_sda */ |
| 246 | {I2C4_SCL, (PTU | IEN | M0)}, /* i2c4_scl */ |
| 247 | {I2C4_SDA, (PTU | IEN | M0)} /* i2c4_sda */ |
| Sricharan | 9310ff7 | 2011-11-15 09:49:55 -0500 | [diff] [blame] | 248 | }; |
| 249 | |
| 250 | const struct pad_conf_entry wkup_padconf_array_non_essential[] = { |
| 251 | {PAD0_SIM_IO, (IEN | M0)}, /* sim_io */ |
| 252 | {PAD1_SIM_CLK, (M0)}, /* sim_clk */ |
| 253 | {PAD0_SIM_RESET, (M0)}, /* sim_reset */ |
| 254 | {PAD1_SIM_CD, (PTU | IEN | M0)}, /* sim_cd */ |
| 255 | {PAD0_SIM_PWRCTRL, (M0)}, /* sim_pwrctrl */ |
| 256 | {PAD1_FREF_XTAL_IN, (M0)}, /* # */ |
| 257 | {PAD0_FREF_SLICER_IN, (M0)}, /* fref_slicer_in */ |
| 258 | {PAD1_FREF_CLK_IOREQ, (M0)}, /* fref_clk_ioreq */ |
| 259 | {PAD0_FREF_CLK0_OUT, (M2)}, /* sys_drm_msecure */ |
| 260 | {PAD1_FREF_CLK3_REQ, (PTU | IEN | M0)}, /* # */ |
| 261 | {PAD0_FREF_CLK3_OUT, (M0)}, /* fref_clk3_out */ |
| 262 | {PAD1_FREF_CLK4_REQ, (PTU | IEN | M0)}, /* # */ |
| 263 | {PAD0_FREF_CLK4_OUT, (M0)}, /* # */ |
| 264 | {PAD0_SYS_NRESPWRON, (M0)}, /* sys_nrespwron */ |
| 265 | {PAD1_SYS_NRESWARM, (M0)}, /* sys_nreswarm */ |
| 266 | {PAD0_SYS_PWR_REQ, (PTU | M0)}, /* sys_pwr_req */ |
| 267 | {PAD1_SYS_PWRON_RESET, (M3)}, /* gpio_wk29 */ |
| 268 | {PAD0_SYS_BOOT6, (IEN | M3)}, /* gpio_wk9 */ |
| 269 | {PAD1_SYS_BOOT7, (IEN | M3)}, /* gpio_wk10 */ |
| 270 | {PAD1_FREF_CLK3_REQ, (M3)}, /* gpio_wk30 */ |
| 271 | {PAD1_FREF_CLK4_REQ, (M3)}, /* gpio_wk7 */ |
| 272 | {PAD0_FREF_CLK4_OUT, (M3)}, /* gpio_wk8 */ |
| 273 | }; |
| 274 | |
| 275 | #endif /* _EVM4430_MUX_DATA_H */ |