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Prafulla Wadaskar62634642009-07-16 20:58:00 +05301/*
2 * (C) Copyright 2009
3 * Marvell Semiconductor <www.marvell.com>
4 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
22 * MA 02110-1301 USA
23 */
24
25#include <common.h>
26#include <miiphy.h>
Lei Wen298ae912011-10-18 20:11:42 +053027#include <asm/arch/cpu.h>
Prafulla Wadaskar62634642009-07-16 20:58:00 +053028#include <asm/arch/kirkwood.h>
29#include <asm/arch/mpp.h>
30#include "sheevaplug.h"
31
32DECLARE_GLOBAL_DATA_PTR;
33
Prafulla Wadaskar44f4d432010-10-20 20:12:27 +053034int board_early_init_f(void)
Prafulla Wadaskar62634642009-07-16 20:58:00 +053035{
36 /*
37 * default gpio configuration
38 * There are maximum 64 gpios controlled through 2 sets of registers
39 * the below configuration configures mainly initial LED status
40 */
41 kw_config_gpio(SHEEVAPLUG_OE_VAL_LOW,
42 SHEEVAPLUG_OE_VAL_HIGH,
43 SHEEVAPLUG_OE_LOW, SHEEVAPLUG_OE_HIGH);
44
45 /* Multi-Purpose Pins Functionality configuration */
46 u32 kwmpp_config[] = {
47 MPP0_NF_IO2,
48 MPP1_NF_IO3,
49 MPP2_NF_IO4,
50 MPP3_NF_IO5,
51 MPP4_NF_IO6,
52 MPP5_NF_IO7,
53 MPP6_SYSRST_OUTn,
54 MPP7_GPO,
55 MPP8_UART0_RTS,
56 MPP9_UART0_CTS,
57 MPP10_UART0_TXD,
58 MPP11_UART0_RXD,
59 MPP12_SD_CLK,
60 MPP13_SD_CMD,
61 MPP14_SD_D0,
62 MPP15_SD_D1,
63 MPP16_SD_D2,
64 MPP17_SD_D3,
65 MPP18_NF_IO0,
66 MPP19_NF_IO1,
67 MPP20_GPIO,
68 MPP21_GPIO,
69 MPP22_GPIO,
70 MPP23_GPIO,
71 MPP24_GPIO,
72 MPP25_GPIO,
73 MPP26_GPIO,
74 MPP27_GPIO,
75 MPP28_GPIO,
76 MPP29_TSMP9,
77 MPP30_GPIO,
78 MPP31_GPIO,
79 MPP32_GPIO,
80 MPP33_GPIO,
81 MPP34_GPIO,
82 MPP35_GPIO,
83 MPP36_GPIO,
84 MPP37_GPIO,
85 MPP38_GPIO,
86 MPP39_GPIO,
87 MPP40_GPIO,
88 MPP41_GPIO,
89 MPP42_GPIO,
90 MPP43_GPIO,
91 MPP44_GPIO,
92 MPP45_GPIO,
93 MPP46_GPIO,
94 MPP47_GPIO,
95 MPP48_GPIO,
96 MPP49_GPIO,
97 0
98 };
99 kirkwood_mpp_conf(kwmpp_config);
Prafulla Wadaskar44f4d432010-10-20 20:12:27 +0530100 return 0;
101}
Prafulla Wadaskar62634642009-07-16 20:58:00 +0530102
Prafulla Wadaskar44f4d432010-10-20 20:12:27 +0530103int board_init(void)
104{
Prafulla Wadaskar62634642009-07-16 20:58:00 +0530105 /*
106 * arch number of board
107 */
108 gd->bd->bi_arch_number = MACH_TYPE_SHEEVAPLUG;
109
110 /* adress of boot parameters */
111 gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
112
113 return 0;
114}
115
Prafulla Wadaskar62634642009-07-16 20:58:00 +0530116#ifdef CONFIG_RESET_PHY_R
117/* Configure and enable MV88E1116 PHY */
118void reset_phy(void)
119{
120 u16 reg;
121 u16 devadr;
122 char *name = "egiga0";
123
124 if (miiphy_set_current_dev(name))
125 return;
126
127 /* command to read PHY dev address */
128 if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
129 printf("Err..%s could not read PHY dev address\n",
130 __FUNCTION__);
131 return;
132 }
133
134 /*
135 * Enable RGMII delay on Tx and Rx for CPU port
136 * Ref: sec 4.7.2 of chip datasheet
137 */
138 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
139 miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);
140 reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
141 miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
142 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
143
144 /* reset the phy */
145 miiphy_reset(name, devadr);
146
147 printf("88E1116 Initialized on %s\n", name);
148}
149#endif /* CONFIG_RESET_PHY_R */