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git01.mediatek.com / filogic / uboot / 38ff13d44b58de7e4e0febf16e02a11971c4e8a8 / . / arch / arm / include / asm / arch-mx6 / imx-regs.h
blob: 6b7589b78a3e76f00bc0c4705160693dbe3088eb [file] [log] [blame]
Jason Liudec11122011-11-25 00:18:02 +0000[diff] [blame]1/*
2 * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
17 */
18
19#ifndef __ASM_ARCH_MX6_IMX_REGS_H__
20#define __ASM_ARCH_MX6_IMX_REGS_H__
21
22#define ROMCP_ARB_BASE_ADDR 0x00000000
23#define ROMCP_ARB_END_ADDR 0x000FFFFF
24#define CAAM_ARB_BASE_ADDR 0x00100000
25#define CAAM_ARB_END_ADDR 0x00103FFF
26#define APBH_DMA_ARB_BASE_ADDR 0x00110000
27#define APBH_DMA_ARB_END_ADDR 0x00117FFF
28#define HDMI_ARB_BASE_ADDR 0x00120000
29#define HDMI_ARB_END_ADDR 0x00128FFF
30#define GPU_3D_ARB_BASE_ADDR 0x00130000
31#define GPU_3D_ARB_END_ADDR 0x00133FFF
32#define GPU_2D_ARB_BASE_ADDR 0x00134000
33#define GPU_2D_ARB_END_ADDR 0x00137FFF
34#define DTCP_ARB_BASE_ADDR 0x00138000
35#define DTCP_ARB_END_ADDR 0x0013BFFF
36
37/* GPV - PL301 configuration ports */
38#define GPV2_BASE_ADDR 0x00200000
39#define GPV3_BASE_ADDR 0x00300000
40#define GPV4_BASE_ADDR 0x00800000
41#define IRAM_BASE_ADDR 0x00900000
42#define SCU_BASE_ADDR 0x00A00000
43#define IC_INTERFACES_BASE_ADDR 0x00A00100
44#define GLOBAL_TIMER_BASE_ADDR 0x00A00200
45#define PRIVATE_TIMERS_WD_BASE_ADDR 0x00A00600
46#define IC_DISTRIBUTOR_BASE_ADDR 0x00A01000
47#define GPV0_BASE_ADDR 0x00B00000
48#define GPV1_BASE_ADDR 0x00C00000
49#define PCIE_ARB_BASE_ADDR 0x01000000
50#define PCIE_ARB_END_ADDR 0x01FFFFFF
51
52#define AIPS1_ARB_BASE_ADDR 0x02000000
53#define AIPS1_ARB_END_ADDR 0x020FFFFF
54#define AIPS2_ARB_BASE_ADDR 0x02100000
55#define AIPS2_ARB_END_ADDR 0x021FFFFF
56#define SATA_ARB_BASE_ADDR 0x02200000
57#define SATA_ARB_END_ADDR 0x02203FFF
58#define OPENVG_ARB_BASE_ADDR 0x02204000
59#define OPENVG_ARB_END_ADDR 0x02207FFF
60#define HSI_ARB_BASE_ADDR 0x02208000
61#define HSI_ARB_END_ADDR 0x0220BFFF
62#define IPU1_ARB_BASE_ADDR 0x02400000
63#define IPU1_ARB_END_ADDR 0x027FFFFF
64#define IPU2_ARB_BASE_ADDR 0x02800000
65#define IPU2_ARB_END_ADDR 0x02BFFFFF
66#define WEIM_ARB_BASE_ADDR 0x08000000
67#define WEIM_ARB_END_ADDR 0x0FFFFFFF
68
69#define MMDC0_ARB_BASE_ADDR 0x10000000
70#define MMDC0_ARB_END_ADDR 0x7FFFFFFF
71#define MMDC1_ARB_BASE_ADDR 0x80000000
72#define MMDC1_ARB_END_ADDR 0xFFFFFFFF
73
74/* Defines for Blocks connected via AIPS (SkyBlue) */
75#define ATZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR
76#define ATZ2_BASE_ADDR AIPS2_ARB_BASE_ADDR
77#define AIPS1_BASE_ADDR AIPS1_ON_BASE_ADDR
78#define AIPS2_BASE_ADDR AIPS2_ON_BASE_ADDR
79
80#define SPDIF_BASE_ADDR (ATZ1_BASE_ADDR + 0x04000)
81#define ECSPI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x08000)
82#define ECSPI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x0C000)
83#define ECSPI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x10000)
84#define ECSPI4_BASE_ADDR (ATZ1_BASE_ADDR + 0x14000)
85#define ECSPI5_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000)
86#define UART1_BASE (ATZ1_BASE_ADDR + 0x20000)
87#define ESAI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
88#define SSI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000)
89#define SSI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000)
90#define SSI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000)
91#define ASRC_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000)
92#define SPBA_BASE_ADDR (ATZ1_BASE_ADDR + 0x3C000)
93#define VPU_BASE_ADDR (ATZ1_BASE_ADDR + 0x40000)
94#define AIPS1_ON_BASE_ADDR (ATZ1_BASE_ADDR + 0x7C000)
95
96#define AIPS1_OFF_BASE_ADDR (ATZ1_BASE_ADDR + 0x80000)
97#define PWM1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x0000)
98#define PWM2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4000)
99#define PWM3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x8000)
100#define PWM4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0xC000)
101#define CAN1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x10000)
102#define CAN2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x14000)
103#define GPT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x18000)
104#define GPIO1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x1C000)
105#define GPIO2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x20000)
106#define GPIO3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x24000)
107#define GPIO4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x28000)
108#define GPIO5_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x2C000)
109#define GPIO6_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x30000)
110#define GPIO7_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000)
111#define KPP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x38000)
112#define WDOG1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x3C000)
113#define WDOG2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x40000)
114#define CCM_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x44000)
115#define ANATOP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x48000)
116#define SNVS_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4C000)
117#define EPIT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x50000)
118#define EPIT2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x54000)
119#define SRC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x58000)
120#define GPC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x5C000)
121#define IOMUXC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x60000)
122#define DCIC1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000)
123#define DCIC2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
124#define DMA_REQ_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
125
126#define AIPS2_ON_BASE_ADDR (ATZ2_BASE_ADDR + 0x7C000)
127#define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000)
128#define CAAM_BASE_ADDR (ATZ2_BASE_ADDR)
129#define ARM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000)
130#define USBOH3_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000)
131#define USBOH3_USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000)
132#define ENET_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x8000)
133#define MLB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
134#define USDHC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x10000)
135#define USDHC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x14000)
136#define USDHC3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x18000)
137#define USDHC4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x1C000)
138#define I2C1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x20000)
139#define I2C2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x24000)
140#define I2C3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x28000)
141#define ROMCP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x2C000)
142#define MMDC_P0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x30000)
143#define MMDC_P1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
144#define WEIM_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x38000)
145#define OCOTP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x3C000)
146#define CSU_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x40000)
147#define IP2APB_PERFMON1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x44000)
148#define IP2APB_PERFMON2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000)
149#define IP2APB_PERFMON3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000)
150#define IP2APB_TZASC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x50000)
151#define IP2APB_TZASC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000)
152#define AUDMUX_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000)
153#define MIPI_CSI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000)
154#define MIPI_DSI_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000)
155#define VDOA_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000)
156#define UART2_BASE (AIPS2_OFF_BASE_ADDR + 0x68000)
157#define UART3_BASE (AIPS2_OFF_BASE_ADDR + 0x6C000)
158#define UART4_BASE (AIPS2_OFF_BASE_ADDR + 0x70000)
159#define UART5_BASE (AIPS2_OFF_BASE_ADDR + 0x74000)
160#define IP2APB_USBPHY1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000)
161#define IP2APB_USBPHY2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000)
162
163#define CHIP_REV_1_0 0x10
164#define IRAM_SIZE 0x00040000
165#define IMX_IIM_BASE OCOTP_BASE_ADDR
Troy Kisky01112132012-02-07 14:08:46 +0000[diff] [blame]166#define FEC_QUIRK_ENET_MAC
Jason Liudec11122011-11-25 00:18:02 +0000[diff] [blame]167
Eric Nelson066263d2012-01-31 07:52:01 +0000[diff] [blame]168#define GPIO_NUMBER(port, index) ((((port)-1)*32)+((index)&31))
169#define GPIO_TO_PORT(number) (((number)/32)+1)
170#define GPIO_TO_INDEX(number) ((number)&31)
171
Jason Liudec11122011-11-25 00:18:02 +0000[diff] [blame]172#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
173#include <asm/types.h>
174
Fabio Estevam04fc1282011-12-20 05:46:31 +0000[diff] [blame]175extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
Jason Liudec11122011-11-25 00:18:02 +0000[diff] [blame]176
177/* System Reset Controller (SRC) */
178struct src {
179 u32 scr;
180 u32 sbmr1;
181 u32 srsr;
182 u32 reserved1[2];
183 u32 sisr;
184 u32 simr;
185 u32 sbmr2;
186 u32 gpr1;
187 u32 gpr2;
188 u32 gpr3;
189 u32 gpr4;
190 u32 gpr5;
191 u32 gpr6;
192 u32 gpr7;
193 u32 gpr8;
194 u32 gpr9;
195 u32 gpr10;
196};
197
Eric Nelson32565c52012-01-31 07:52:04 +0000[diff] [blame]198/* ECSPI registers */
199struct cspi_regs {
200 u32 rxdata;
201 u32 txdata;
202 u32 ctrl;
203 u32 cfg;
204 u32 intr;
205 u32 dma;
206 u32 stat;
207 u32 period;
208};
209
210/*
211 * CSPI register definitions
212 */
213#define MXC_ECSPI
214#define MXC_CSPICTRL_EN (1 << 0)
215#define MXC_CSPICTRL_MODE (1 << 1)
216#define MXC_CSPICTRL_XCH (1 << 2)
217#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
218#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
219#define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12)
220#define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8)
221#define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18)
222#define MXC_CSPICTRL_MAXBITS 0xfff
223#define MXC_CSPICTRL_TC (1 << 7)
224#define MXC_CSPICTRL_RXOVF (1 << 6)
225#define MXC_CSPIPERIOD_32KHZ (1 << 15)
226#define MAX_SPI_BYTES 32
227
228/* Bit position inside CTRL register to be associated with SS */
229#define MXC_CSPICTRL_CHAN 18
230
231/* Bit position inside CON register to be associated with SS */
232#define MXC_CSPICON_POL 4
233#define MXC_CSPICON_PHA 0
234#define MXC_CSPICON_SSPOL 12
235#define MXC_SPI_BASE_ADDRESSES \
236 ECSPI1_BASE_ADDR, \
237 ECSPI2_BASE_ADDR, \
238 ECSPI3_BASE_ADDR, \
239 ECSPI4_BASE_ADDR, \
240 ECSPI5_BASE_ADDR
241
Jason Liudec11122011-11-25 00:18:02 +0000[diff] [blame]242struct iim_regs {
243 u32 ctrl;
244 u32 ctrl_set;
245 u32 ctrl_clr;
246 u32 ctrl_tog;
247 u32 timing;
248 u32 rsvd0[3];
249 u32 data;
250 u32 rsvd1[3];
251 u32 read_ctrl;
252 u32 rsvd2[3];
253 u32 fuse_data;
254 u32 rsvd3[3];
255 u32 sticky;
256 u32 rsvd4[3];
257 u32 scs;
258 u32 scs_set;
259 u32 scs_clr;
260 u32 scs_tog;
261 u32 crc_addr;
262 u32 rsvd5[3];
263 u32 crc_value;
264 u32 rsvd6[3];
265 u32 version;
Jason Liubf651aa2011-12-19 02:38:13 +0000[diff] [blame]266 u32 rsvd7[0xdb];
Jason Liudec11122011-11-25 00:18:02 +0000[diff] [blame]267
268 struct fuse_bank {
269 u32 fuse_regs[0x20];
270 } bank[15];
271};
272
273struct fuse_bank4_regs {
274 u32 sjc_resp_low;
275 u32 rsvd0[3];
276 u32 sjc_resp_high;
277 u32 rsvd1[3];
278 u32 mac_addr_low;
279 u32 rsvd2[3];
280 u32 mac_addr_high;
281 u32 rsvd3[0x13];
282};
283
Jason Liubb25e072012-01-10 00:52:59 +0000[diff] [blame]284struct aipstz_regs {
285 u32 mprot0;
286 u32 mprot1;
287 u32 rsvd[0xe];
288 u32 opacr0;
289 u32 opacr1;
290 u32 opacr2;
291 u32 opacr3;
292 u32 opacr4;
293};
294
Jason Liudec11122011-11-25 00:18:02 +0000[diff] [blame]295#endif /* __ASSEMBLER__*/
296#endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */